J
Jan Decaluwe
Mike said:My advice applies only to VHDL and FPGAs.
I know very little about ASICs and Verilog.
Try it and see. I found no substantial difference
using Easics vs leo or synplicity on parallel
16 and 32 bit FCS checkers for an FPGA target.
Try and see is definitely the good advice.
My experience dates back several years, with Synopsys -
other synthesis tools / versions may behave differently,
especially if they would contain xor-specific optimizations,
as they perfectly could.
Also, for the record: a "stand-alone" experiment with
only the CRC functions is not sufficient to judge well.
The functions can and will be used in a context -
I remember that the difference became especially significant
within larger modules and for large bit
widths (e.g. 32) and large poly's (e.g. Ethernet).
However - if there's no significant difference, then
there is definitely no reason to use a specialized solution.
Regards, Jan