Signal delay compilation error - Please Help

Discussion in 'VHDL' started by Daku, Dec 17, 2009.

  1. Daku

    Daku Guest

    Could some VHDL guru point out what I might be doing incorrectly ?
    1. The following code compiles perfectly:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_arith.ALL;
    use IEEE.NUMERIC_STD.ALL;

    ENTITY testclock IS
    PORT (inclk : in std_logic;
    outclk : out std_logic);
    END testclock;

    ARCHITECTURE dftest OF testclock IS
    SIGNAL local : std_logic := '0';

    BEGIN

    proc1 : PROCESS(inclk)
    BEGIN
    IF RISING_EDGE(inclk) THEN
    local <= inclk;
    END IF;
    END PROCESS proc1;

    proc2 : PROCESS(inclk)
    BEGIN
    IF FALLING_EDGE(inclk) THEN
    outclk <= local;
    END IF;
    END PROCESS proc2;

    END dftest;

    2. A small modification to proc2 as :
    proc2 : PROCESS(inclk)
    BEGIN
    IF FALLING_EDGE(inclk) THEN
    outclk <= local'DELAYED(1000ns);
    --outclk <= TRANSPORT local AFTER 1000ns;
    END IF;
    END PROCESS proc2;

    produces the error message:
    vbl_bcomp_y.y 4463 : Error 18 line 22 in file testclock :illegal
    concurrent statement

    3. In Verilog, one can have a variable period (alternatively variable
    frequency) clock as:
    always
    # (fixed_half_period) clock = 0;
    # (fixed_half_period + variable_delay) = 1;
    where variable_delay can be generated using a standard distribution,
    as $dist_exponential

    Is there a similar way to control clock periods in VHDL ?

    Any hints, suggestions would be of invaluable. Thanks in advance for
    your help.
     
    Daku, Dec 17, 2009
    #1
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  2. Daku

    Tricky Guest

    On 17 Dec, 05:50, Daku <> wrote:
    > Could some VHDL guru point out what I might be doing incorrectly ?
    > 1. The following code compiles perfectly:
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_arith.ALL;
    > use IEEE.NUMERIC_STD.ALL;



    First point - dont use std_logic_arith and numeric_std. Use one or the
    other, preferably numeric_std.

    >
    > ENTITY testclock IS
    >  PORT (inclk  : in std_logic;
    >        outclk : out std_logic);
    > END testclock;
    >
    > ARCHITECTURE dftest OF testclock IS
    >   SIGNAL local : std_logic := '0';
    >
    >   BEGIN
    >
    >      proc1 : PROCESS(inclk)
    >       BEGIN
    >        IF RISING_EDGE(inclk) THEN
    >          local <= inclk;
    >        END IF;
    >      END PROCESS proc1;
    >
    >      proc2 : PROCESS(inclk)
    >       BEGIN
    >        IF FALLING_EDGE(inclk) THEN
    >          outclk <= local;
    >        END IF;
    >      END PROCESS proc2;
    >
    > END dftest;
    >
    > 2. A small modification to proc2 as :
    > proc2 : PROCESS(inclk)
    >       BEGIN
    >        IF FALLING_EDGE(inclk) THEN
    >          outclk <= local'DELAYED(1000ns);
    >          --outclk <= TRANSPORT local AFTER 1000ns;
    >        END IF;
    >      END PROCESS proc2;
    >
    > produces the error message:
    > vbl_bcomp_y.y 4463 : Error 18 line 22 in file testclock :illegal
    > concurrent statement
    >
    > 3. In Verilog, one can have a variable period (alternatively variable
    > frequency) clock as:
    > always
    >  # (fixed_half_period) clock = 0;
    >  # (fixed_half_period + variable_delay) = 1;
    > where variable_delay can be generated using a standard distribution,
    > as $dist_exponential
    >
    > Is there a similar way to control clock periods in VHDL ?
    >
    > Any hints, suggestions would be of invaluable. Thanks in advance for
    > your help.



    How are you trying to compile this? This is not synthesisable code, so
    it will only run in a simulator.
     
    Tricky, Dec 17, 2009
    #2
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  3. On Wed, 16 Dec 2009 21:50:15 -0800 (PST), Daku wrote:

    > proc1 : PROCESS(inclk)
    > BEGIN
    > IF RISING_EDGE(inclk) THEN
    > local <= inclk;
    > END IF;
    > END PROCESS proc1;


    I assume you're aware that this will drive "local" to '1' on
    the first rising edge, and then leave it at '1' permanently?

    >2. A small modification to proc2 as :
    >proc2 : PROCESS(inclk)
    > BEGIN
    > IF FALLING_EDGE(inclk) THEN
    > outclk <= local'DELAYED(1000ns);
    > --outclk <= TRANSPORT local AFTER 1000ns;
    > END IF;
    > END PROCESS proc2;
    >
    >produces the error message:
    >vbl_bcomp_y.y 4463 : Error 18 line 22 in file testclock :illegal
    >concurrent statement


    Where is line 22? I don't see any illegal concurrent statement
    here. As Tricky said, perhaps you're trying to compile this
    simulation-only code with a synthesis tool?

    However, there is an error. In VHDL it's mandatory to have a
    space between time number and units: "100 ns", NOT "100ns".
    Some tools tolerate it without a space, but they should at least
    give a warning message.

    >Is there a similar way to control clock periods in VHDL ?


    variable timeA, timeB: time;
    ...
    timeA = 100 ns;
    timeB = timeA / 3;
    wait for (timeA + timeB + ...);
    sigA <= sigB after (timeA + 5 ns);

    But NOT

    sigA <= sigB'delayed(timeB);

    because the argument to 'delayed must be a constant expression.
    --
    Jonathan Bromley
     
    Jonathan Bromley, Dec 17, 2009
    #3
  4. On Wed, 16 Dec 2009 21:50:15 -0800 (PST), Daku <> wrote:


    >Is there a similar way to control clock periods in VHDL ?






    I have used a DDS in a similar way to this here to sweep a carrier
    across the pass/stop band of a FIR filter, plotting the true
    filter response in dB over f in Modelsim. :)


    regards, Gerhard





    file clk_and_rst.vhd:
    ------------------------------------
    -- (c) jul 2007 Gerhard Hoffmann, ghf at hoffmann - hochfrequenz . de
    -- open source under BSD conditions
    -- :set tabstop=4
    -- canonic location: /lib/vhdl/tb/clk_and_rst/clk_and_rst.vhd
    --
    -- Solution to an everyday problem.
    -- This module produces a clock for a simulation with selectable frequency
    -- and a reset signal with selectable width.
    -- The clock duty cycle is 1:1.
    -- The reset is active from the beginning and removed synchronously shortly
    -- after a rising clock edge.
    --
    -- setting verbose to true gives some diagnostics.
    --
    -- Make sure that your simulator has a time resolution of at least 1 ps.
    -- For modelsim, this is set up by the various modelsim.ini files
    -- and/or the project file (foobar.mpf)


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;

    entity clk_and_rst is
    generic (
    verbose: boolean := false
    );
    port (

    clock_frequency: in real := 100.0e6;
    min_resetwidth: in time := 12 ns; -- minimum resetwidth, is synchronized to clk

    clk: out std_logic;
    rst: out std_logic
    );
    end entity clk_and_rst;


    --
    architecture rtl of clk_and_rst is

    signal iclk: std_logic := '0'; -- entity-internal clk and rst
    signal irst: std_logic := '1';
    signal halfcycle: time := 0 ps;





    -- The clock frequency is given in Hz in floating point format.
    -- compute the equivalent half cycle time.

    function frequency2halfcycle(f: real; verbose: boolean) return time is

    variable picoseconds: real;
    variable retval: time;

    begin
    assert f > 1.0e-10
    report "clk_and_rst.vhd: requested clock frequency is unreasonably low or even negative - danger of 1/0.0"
    severity error;

    picoseconds := (0.5 / f ) / 1.0e-12;
    retval := integer(picoseconds) * 1 ps;

    if verbose then
    report "function frequency2halfcycle in clk_and_rst.vhd: picoseconds = " & real'image(picoseconds);
    report "halfcycle = " & time'image(retval);
    end if;

    assert retval > 0 ps
    report "frequency2halfcycle: length of halfcycle truncated to 0 ps. "
    & "Set simulator resolution to 1 ps or smaller in modelsim.ini or foobar.mpf"
    severity error;

    return retval;
    end;


    ----------------------------------------------------------------------------------------------------
    begin

    --
    -- generate the internal system clock


    u_determine_halfcycle: process (clock_frequency) is
    begin
    halfcycle <= frequency2halfcycle(clock_frequency, verbose);
    end process u_determine_halfcycle;


    u_sysclock: process is
    begin
    wait for halfcycle;
    iclk <= '1';

    wait for halfcycle;
    iclk <= '0';
    end process u_sysclock;

    clk <= iclk;


    --
    -- generate internal reset

    u_rst: process is
    begin
    irst <= '1';
    wait for min_resetwidth;
    wait until rising_edge(iclk);
    irst <= '0';
    wait; -- forever
    end process u_rst;

    rst <= irst;

    end architecture rtl;

    ----------------------------------------

    file clk_and_rst_tb.vhd:
    ----------------------------------------
    -- testbed for entity clk_and_reset.vhd
    -- (c) jul 2007 Gerhard Hoffmann, ghf at hoffmann - hochfrequenz . de
    -- open source under BSD conditions
    -- slightly modified 2009-mar-23

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.numeric_std.all;


    entity clk_and_rst_tb is
    end entity clk_and_rst_tb;

    --
    architecture rtl of clk_and_rst_tb is

    component clk_and_rst is
    generic (
    verbose: boolean := false
    );
    port (
    clock_frequency: in real := 100.0e6;
    min_resetwidth: in time := 12 ns; -- minimum rese twidth, is synchronized to clk

    clk: out std_logic;
    rst: out std_logic
    );
    end component;

    signal clk: std_logic;
    signal rst: std_logic;
    signal frequency: real;

    begin


    frequency <= 100.0e6, 50.0e6 after 200 ns, 10.0e6 after 400 ns;

    uut: clk_and_rst
    generic map(
    verbose => true
    )
    port map(

    clock_frequency => frequency,
    min_resetwidth => 153 ns,

    clk => clk,
    rst => rst
    );
     
    Gerhard Hoffmann, Dec 17, 2009
    #4
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