Signal Initialization Confusion

Discussion in 'VHDL' started by Analog_Guy, Aug 11, 2006.

  1. Analog_Guy

    Analog_Guy Guest

    I have a really simple setup to test the initialization of signals, and
    am a little confused as to the simulator results.

    When the compiled design is loaded into the simulator (ModelSim), sig2
    is initialized at 'U' and sig3 is initialized at '1'.

    sig2 is initialized in the signal declaration part of the top-level
    file, whereas sig3 is initialized in the entity port. Why is there a
    difference in the simulator? Here is the code:

    CLIENT:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY client IS
    PORT(
    sig2 : OUT std_logic;
    sig3 : OUT std_logic := '1'
    );
    END client ;
    --
    ARCHITECTURE struct OF client IS
    BEGIN
    END struct;




    SERVER:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY server IS
    PORT(
    sig2 : IN std_logic;
    sig3 : IN std_logic
    );
    END server ;
    --
    ARCHITECTURE struct OF server IS
    BEGIN
    END struct;





    TOP-LEVEL:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY test_top IS
    END test_top ;

    LIBRARY test;

    ARCHITECTURE struct OF test_top IS
    -- Internal signal declarations
    SIGNAL sig2 : std_logic := '1';
    SIGNAL sig3 : std_logic;

    -- Component Declarations
    COMPONENT client
    PORT (
    sig2 : OUT std_logic ;
    sig3 : OUT std_logic := '1'
    );
    END COMPONENT;
    COMPONENT server
    PORT (
    sig2 : IN std_logic ;
    sig3 : IN std_logic
    );
    END COMPONENT;

    BEGIN
    -- Instance port mappings.
    I0 : client
    PORT MAP (
    sig2 => sig2,
    sig3 => sig3
    );
    I1 : server
    PORT MAP (
    sig2 => sig2,
    sig3 => sig3
    );

    END struct;
     
    Analog_Guy, Aug 11, 2006
    #1
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  2. Analog_Guy

    Ajeetha Guest

    Your sig2 is an output from client model and hence that will win over
    the local signal initialization done at top_level. Since sig2 is not
    being driven by your client model, it stays at U.


    Sig3 is initialized by the client model's output itself.

    Does that explain?

    Regards
    Ajeetha, CVC
    www.noveldv.com
    * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
    h**p://www.systemverilog.us/
    * SystemVerilog Assertions Handbook
    * Using PSL/Sugar


    Analog_Guy wrote:
    > I have a really simple setup to test the initialization of signals, and
    > am a little confused as to the simulator results.
    >
     
    Ajeetha, Aug 12, 2006
    #2
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