Signals too slow

Discussion in 'VHDL' started by jcafaro10, Sep 28, 2009.

  1. jcafaro10

    jcafaro10

    Joined:
    Nov 12, 2007
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    I'm having a problem getting the timing right on a simple program I'm working on in VHDL. Basically I have some data that I want to store to memory and when a valid signal is high the data is supposed to be written to the starting address, which then gets incremented. The problem is that theres an extra clock cycle where my address is being figured out, so my first data piece gets overwritten, and I can't quite figure out why.

    Here's what I've got so far:
    Code (Text):

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    entity framestore is
        port
        (
            clk,reset : in std_logic;
            input: in std_logic_vector(3 downto 0);
            valid: in std_logic;
            readEN: in std_logic;
            rwaddressstart: in std_logic_vector(14 downto 0);
            output : out std_logic_vector(3 downto 0);
            addressout: out std_logic_vector(14 downto 0);
            holdout: out std_logic_vector(3 downto 0);
            validreout: out std_logic;
            readreout: out std_logic
        );
    end framestore;

    architecture structure of framestore is
        signal hold: std_logic_vector(3 downto 0);
        signal address: std_logic_vector(14 downto 0);
        signal tempvalid: std_logic;
        signal tempread: std_logic;
        signal readEn_RE: boolean;
        signal valid_RE: boolean;
       
        component ram4bits is
        PORT
        (
            address     : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
            clock       : IN STD_LOGIC  := '1';
            data        : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
            wren        : IN STD_LOGIC ;
            q       : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
        );
        end component;
    begin  
        process(clk,reset,valid,readEn)
        begin
            if(reset = '1') then
                address <= "000000000000000";
            elsif(clk'event and clk = '1') then
                if(valid_RE or readEn_RE) then
                    address <= rwaddressstart;
                elsif(valid = '1' or readEn = '1') then
                    address <= address + '1';
                end if;
            elsif(clk'event and clk = '0') then
                tempread <= readEn;
                tempvalid <= valid;
            end if;
        end process;
       
        store: ram4bits port map(address,clk,input,valid,hold);
       
        readEn_RE <= tempread = '0' and readEn = '1';
        valid_RE <= tempvalid = '0' and valid = '1';
        output <= hold when readEn = '1' else "0000";
       
        validreout <= '1' when valid_RE else '0';
        readreout <= '1' when readEn_RE else '0';
        addressout <= address;
        holdout <= hold;
       
    end structure;
     
     
    jcafaro10, Sep 28, 2009
    #1
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