Signed operation in VHDL

Discussion in 'VHDL' started by sridar, Aug 29, 2010.

  1. sridar

    sridar

    Joined:
    Jun 5, 2007
    Messages:
    51
    Hi all,

    This topic on signed operation in VHDL puzzles me a lot. first of all, i tried the subtraction operation using unsigned data type, then with the signed data type. Both gives the same output in simulation. can anyone please explain me this?
    sridar, Aug 29, 2010
    #1
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