std_logic_vector(0 downto 0)

Discussion in 'VHDL' started by Brad Smallridge, Nov 12, 2004.

  1. The Xilinx core generator generates std_logic_vector(0 downto 0) on some
    parts like a BUSMUX. How do you "cast" this IO so that it can be connected
    to std_logic without errors?

    Brad Smallridge
    b r a d @ a i v i s i o n . c o m
     
    Brad Smallridge, Nov 12, 2004
    #1
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  2. Brad,

    if

    a : std_logic_vector(0 downto 0) ;

    and

    b : std_logic ;

    then

    b <= a(0) ;

    Hope this help,

    Andrea


    "Brad Smallridge" <> wrote in message
    news:...
    > The Xilinx core generator generates std_logic_vector(0 downto 0) on some
    > parts like a BUSMUX. How do you "cast" this IO so that it can be

    connected
    > to std_logic without errors?
    >
    > Brad Smallridge
    > b r a d @ a i v i s i o n . c o m
    >
    >
    >
     
    Andrea Sabatini, Nov 12, 2004
    #2
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  3. Brad Smallridge

    Antti Lukats Guest

    "Brad Smallridge" <> wrote in message
    news:...
    > The Xilinx core generator generates std_logic_vector(0 downto 0) on some
    > parts like a BUSMUX. How do you "cast" this IO so that it can be

    connected
    > to std_logic without errors?
    >
    > Brad Smallridge
    > b r a d @ a i v i s i o n . c o m


    signal_not_vector <= signal_vector_size0(0);

    maybe there is other way, but I do the above if needed.
    Antti
     
    Antti Lukats, Nov 12, 2004
    #3
  4. Hi!

    Andrea Sabatini wrote:

    > a : std_logic_vector(0 downto 0) ;
    > b : std_logic ;

    [...]
    > b <= a(0) ;


    Alternatively:

    (0 => b) <= a;

    (choose whichever seems more appropriate). Similarly, if `a' is a port,
    you can use individual association:

    a(0) => b

    or associate the port as a whole:

    a => (0 => b)

    in the port map aspect of the component instantiation statement.

    --
    Michael "Tired" Riepe <-hannover.de>
    "All I wanna do is have a little fun before I die"
     
    Michael Riepe, Nov 12, 2004
    #4
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