std_logic_vector Array Input

[Brad Smallridge]

I have some modules that accept a matrix of video bits.
These are binarized windows of one bit per pixel.
Presently I input the rows of bits using a separate
std_logic_vector for each row of bits. I would like to
clean this code up and input an array of std_logic_vector's.
How do I do this?
Do I need some sort of package that declares the array?
And are there any examples where the dimensions are unspecified.

Thanks,

Brad Smallridge
Ai Vision

 

[weber]

I have some modules that accept a matrix of video bits.
These are binarized windows of one bit per pixel.
Presently I input the rows of bits using a separate
std_logic_vector for each row of bits. I would like to
clean this code up and input an array of std_logic_vector's.
How do I do this?
Do I need some sort of package that declares the array?
And are there any examples where the dimensions are unspecified.

Thanks,

Brad Smallridge
Ai Vision

Hi!
You just need to declare a new type like this. It would be interesting
to put it into your pkg.vhd so any file can use it:

type array8 is array (integer range <>) of std_logic_vector(7 downto
0);

So you see one dimension is fixed and the other you specify in the
declaration.
Maybe there is a better way that I don't know about....

Then you would declare your signals and ports normally:

port (
myvideodata : in array8(7 downto 0);
...
)

So here you have 64 bits as 8x8.
If you need to access a single bit from that array you can use (x)(y)
I guess...

Did this help you ?

Cheers,
weber

 

[Torsten Landschoff]

You just need to declare a new type like this. It would be interesting
to put it into your pkg.vhd so any file can use it:

type array8 is array (integer range <>) of std_logic_vector(7 downto
0);

So you see one dimension is fixed and the other you specify in the
declaration.
Maybe there is a better way that I don't know about....

You can even define a n-dimensional array with unconstrained ranges,
like this:

type video_bits is array(integer range <>, integer range <>) of
std_logic;

Instances can be declared like this:

port ( video_data : in video_bits(7 downto 0, 7 downto 0) );

for example. Not sure if this is supported by all VHDL tools, but XST
accepts it at least.

Greetings

Torsten

 

[Ralf Hildebrandt]

Brad Smallridge schrieb:

I have some modules that accept a matrix of video bits.
These are binarized windows of one bit per pixel.
Presently I input the rows of bits using a separate
std_logic_vector for each row of bits. I would like to
clean this code up and input an array of std_logic_vector's.

Using 2D-Arrays as I/O signals _may_ be a problem for some synthesis
tools. If you encounter problems, create one large std_ulogic_vector and
put all elements in a line into it.
(Every n-dimensional structure can be mapped to an (n-1)-dimensional
structure concatenating the elements.)


Ralf

 

[KJ]

Using 2D-Arrays as I/O signals _may_ be a problem for some synthesis
tools. If you encounter problems,

KJ: Open a service request to the supplier of the synthesis tool
complaining about their lack of support for two dimensional arrays.
Mention to them that both Quartus and Modelsim handle them properly
(tends to get somewhat more attention when you point out things that
their competitors are doing that they can not). Also add that you'll
consider their current lack of support for what is now a 20 year old
feature of the language when deciding whether to continue using their
parts and/or tools.

At this point, you'll have done your part to help the supplier improve
their tools but don't bother holding your breath waiting for the fix
so continue on with what Brad posted....

 

[Andy]

KJ: Open a service request to the supplier of the synthesis tool
complaining about their lack of support for two dimensional arrays.
Mention to them that both Quartus and Modelsim handle them properly
(tends to get somewhat more attention when you point out things that
their competitors are doing that they can not). Also add that you'll
consider their current lack of support for what is now a 20 year old
feature of the language when deciding whether to continue using their
parts and/or tools.

At this point, you'll have done your part to help the supplier improve
their tools but don't bother holding your breath waiting for the fix
so continue on with what Brad posted....

You can declare an array of std_logic_vectors, where the number of
vectors is unconstrained, but the size of each vector must be
constrained. This method works with virtually any synthesis tool. If
these are primary IO of the FPGA, the suggestion to code it with one
long slv is probably best.

Andy