std_logic_vector Array Input

Discussion in 'VHDL' started by Brad Smallridge, Feb 22, 2007.

  1. I have some modules that accept a matrix of video bits.
    These are binarized windows of one bit per pixel.
    Presently I input the rows of bits using a separate
    std_logic_vector for each row of bits. I would like to
    clean this code up and input an array of std_logic_vector's.
    How do I do this?
    Do I need some sort of package that declares the array?
    And are there any examples where the dimensions are unspecified.

    Thanks,

    Brad Smallridge
    Ai Vision
     
    Brad Smallridge, Feb 22, 2007
    #1
    1. Advertising

  2. Brad Smallridge

    weber Guest

    On 22 fev, 16:49, "Brad Smallridge" <>
    wrote:
    > I have some modules that accept a matrix of video bits.
    > These are binarized windows of one bit per pixel.
    > Presently I input the rows of bits using a separate
    > std_logic_vector for each row of bits. I would like to
    > clean this code up and input an array of std_logic_vector's.
    > How do I do this?
    > Do I need some sort of package that declares the array?
    > And are there any examples where the dimensions are unspecified.
    >
    > Thanks,
    >
    > Brad Smallridge
    > Ai Vision


    Hi!
    You just need to declare a new type like this. It would be interesting
    to put it into your pkg.vhd so any file can use it:

    type array8 is array (integer range <>) of std_logic_vector(7 downto
    0);

    So you see one dimension is fixed and the other you specify in the
    declaration.
    Maybe there is a better way that I don't know about....

    Then you would declare your signals and ports normally:

    port (
    myvideodata : in array8(7 downto 0);
    ...
    )

    So here you have 64 bits as 8x8.
    If you need to access a single bit from that array you can use (x)(y)
    I guess...

    Did this help you ?

    Cheers,
    weber
     
    weber, Feb 22, 2007
    #2
    1. Advertising

  3. On Feb 22, 9:14 pm, "weber" <> wrote:

    > You just need to declare a new type like this. It would be interesting
    > to put it into your pkg.vhd so any file can use it:
    >
    > type array8 is array (integer range <>) of std_logic_vector(7 downto
    > 0);
    >
    > So you see one dimension is fixed and the other you specify in the
    > declaration.
    > Maybe there is a better way that I don't know about....


    You can even define a n-dimensional array with unconstrained ranges,
    like this:

    type video_bits is array(integer range <>, integer range <>) of
    std_logic;

    Instances can be declared like this:

    port ( video_data : in video_bits(7 downto 0, 7 downto 0) );

    for example. Not sure if this is supported by all VHDL tools, but XST
    accepts it at least.

    Greetings

    Torsten
     
    Torsten Landschoff, Feb 23, 2007
    #3
  4. Brad Smallridge schrieb:


    > I have some modules that accept a matrix of video bits.
    > These are binarized windows of one bit per pixel.
    > Presently I input the rows of bits using a separate
    > std_logic_vector for each row of bits. I would like to
    > clean this code up and input an array of std_logic_vector's.


    Using 2D-Arrays as I/O signals _may_ be a problem for some synthesis
    tools. If you encounter problems, create one large std_ulogic_vector and
    put all elements in a line into it.
    (Every n-dimensional structure can be mapped to an (n-1)-dimensional
    structure concatenating the elements.)


    Ralf
     
    Ralf Hildebrandt, Feb 23, 2007
    #4
  5. Brad Smallridge

    KJ Guest

    On Feb 23, 9:41 am, Ralf Hildebrandt <> wrote:
    > Brad Smallridge schrieb:
    >
    > > I have some modules that accept a matrix of video bits.
    > > These are binarized windows of one bit per pixel.
    > > Presently I input the rows of bits using a separate
    > > std_logic_vector for each row of bits. I would like to
    > > clean this code up and input an array of std_logic_vector's.

    >
    > Using 2D-Arrays as I/O signals _may_ be a problem for some synthesis
    > tools. If you encounter problems,


    KJ: Open a service request to the supplier of the synthesis tool
    complaining about their lack of support for two dimensional arrays.
    Mention to them that both Quartus and Modelsim handle them properly
    (tends to get somewhat more attention when you point out things that
    their competitors are doing that they can not). Also add that you'll
    consider their current lack of support for what is now a 20 year old
    feature of the language when deciding whether to continue using their
    parts and/or tools.

    At this point, you'll have done your part to help the supplier improve
    their tools but don't bother holding your breath waiting for the fix
    so continue on with what Brad posted....

    > create one large std_ulogic_vector and
    > put all elements in a line into it.
    > (Every n-dimensional structure can be mapped to an (n-1)-dimensional
    > structure concatenating the elements.)
    >
    > Ralf
     
    KJ, Feb 23, 2007
    #5
  6. Brad Smallridge

    Andy Guest

    On Feb 23, 11:05 am, "KJ" <> wrote:
    > On Feb 23, 9:41 am, Ralf Hildebrandt <> wrote:
    >
    > > Brad Smallridge schrieb:

    >
    > > > I have some modules that accept a matrix of video bits.
    > > > These are binarized windows of one bit per pixel.
    > > > Presently I input the rows of bits using a separate
    > > > std_logic_vector for each row of bits. I would like to
    > > > clean this code up and input an array of std_logic_vector's.

    >
    > > Using 2D-Arrays as I/O signals _may_ be a problem for some synthesis
    > > tools. If you encounter problems,

    >
    > KJ: Open a service request to the supplier of the synthesis tool
    > complaining about their lack of support for two dimensional arrays.
    > Mention to them that both Quartus and Modelsim handle them properly
    > (tends to get somewhat more attention when you point out things that
    > their competitors are doing that they can not). Also add that you'll
    > consider their current lack of support for what is now a 20 year old
    > feature of the language when deciding whether to continue using their
    > parts and/or tools.
    >
    > At this point, you'll have done your part to help the supplier improve
    > their tools but don't bother holding your breath waiting for the fix
    > so continue on with what Brad posted....
    >
    > > create one large std_ulogic_vector and
    > > put all elements in a line into it.
    > > (Every n-dimensional structure can be mapped to an (n-1)-dimensional
    > > structure concatenating the elements.)

    >
    > > Ralf


    You can declare an array of std_logic_vectors, where the number of
    vectors is unconstrained, but the size of each vector must be
    constrained. This method works with virtually any synthesis tool. If
    these are primary IO of the FPGA, the suggestion to code it with one
    long slv is probably best.

    Andy
     
    Andy, Feb 26, 2007
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Willem Oosthuizen

    Array of std_logic_vector

    Willem Oosthuizen, Jul 9, 2003, in forum: VHDL
    Replies:
    3
    Views:
    35,593
    mathukutty
    Feb 26, 2010
  2. Brandon
    Replies:
    2
    Views:
    5,109
    Brandon
    Jul 18, 2005
  3. vince00001
    Replies:
    3
    Views:
    2,654
    quantum_dot
    Jun 6, 2007
  4. Thomas Rouam
    Replies:
    6
    Views:
    1,134
  5. Will
    Replies:
    1
    Views:
    846
    joris
    Mar 10, 2009
Loading...

Share This Page