std_logic_vector to unsigned conversion

Discussion in 'VHDL' started by Al, Nov 8, 2006.

  1. Al

    Al Guest

    Hi guys,
    I just had a disappointing problem, my code had something like:

    vectorA <= unsigned (vectorB);

    where ieee.std_logic_unsigned.all had been included in the library
    declaration.

    Unfortunately vectorA and vectorB where different in lenght, to be
    precise vectorB was shorter than vectorA.
    Synplify didn't complain anything, no errors, no warnings related to it
    (that I noticed, at least), but what had been implemented was a vector
    longer than required which turned out in a counter that will never reach
    the vectorA value and will roll forever!
    Is there any better way to convert std_logic_vector to unsigned with a
    less clever function, but at least more reliable?

    Thanks a lot

    Al




    --
    Alessandro Basili
    CERN, PH/UGC
    Hardware Designer
     
    Al, Nov 8, 2006
    #1
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  2. Al

    Guest

    Hi

    Try with ieee.numeric_std.all instead ieee.std_logic_unsigned.all...
     
    , Nov 8, 2006
    #2
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  3. Al

    KJ Guest

    "Al" <> wrote in message
    news:eisgqc$ga2$...
    > Hi guys,
    > I just had a disappointing problem, my code had something like:
    >
    > vectorA <= unsigned (vectorB);
    >
    > where ieee.std_logic_unsigned.all had been included in the library
    > declaration.
    >
    > Unfortunately vectorA and vectorB where different in lenght, to be precise
    > vectorB was shorter than vectorA.
    > Synplify didn't complain anything, no errors, no warnings related to it
    > (that I noticed, at least), but what had been implemented was a vector
    > longer than required which turned out in a counter that will never reach
    > the vectorA value and will roll forever!
    > Is there any better way to convert std_logic_vector to unsigned with a
    > less clever function, but at least more reliable?
    >


    First of all, use a simulator. My interpretation of your code from your
    description is...
    ....
    signal vectorA: unsigned(7 downto 0); -- Some size vector, by your
    assignment statement it must've been unsigned
    signal vectorB: std_logic_vector(6 downto 0); -- Some different sized
    vector, by your assignment it must not have been unsigned
    begin
    vectorA <= unsigned (vectorB);
    .....

    Surprising that Synplify doesn't complain, but Modelsim gives the following
    error (not warning) which is expected since the vectors are different sizes.

    Error:
    C:/Sim/ZPOC_Sim/HDL/ZFpga_Common/Avl_Track_Controller/Track_Controller/Track_Controller.vhd(265):
    Length of expected is 8; length of actual is 7.

    Assuming that the vectors are the size that you really do want them to be
    then the proper assignment is...

    vectorA <= ieee.numeric_std.resize(unsigned(vectorB), vectorA'length);
    or
    vectorA <= resize(unsigned(vectorB), vectorA'length);
    if you've already got a "use ieee.numeric_std.all" statement in your code.

    KJ
     
    KJ, Nov 8, 2006
    #3
  4. Al

    Al Guest

    KJ wrote:
    >
    > First of all, use a simulator.


    I was using it, but the testbench hided the error because wasn't
    properly designed.

    > My interpretation of your code from your
    > description is...
    > ...
    > signal vectorA: unsigned(7 downto 0); -- Some size vector, by your
    > assignment statement it must've been unsigned
    > signal vectorB: std_logic_vector(6 downto 0); -- Some different sized
    > vector, by your assignment it must not have been unsigned
    > begin
    > vectorA <= unsigned (vectorB);
    > ....


    correct.

    >
    > Surprising that Synplify doesn't complain, but Modelsim gives the following
    > error (not warning) which is expected since the vectors are different sizes.


    As I said, I'm not sure that Synplify didn't complain because I didn't
    check carefully all the type of warnings (basically I have a lot of them
    complaining because not all the global registers I declared in the
    package were used by each entity, but this didn't really bother me).
    >
    > Error:
    > C:/Sim/ZPOC_Sim/HDL/ZFpga_Common/Avl_Track_Controller/Track_Controller/Track_Controller.vhd(265):
    > Length of expected is 8; length of actual is 7.
    >

    Once synthesized I usually simulate a post-synthesis and a post-layout
    file, which will not show the problem anymore

    > Assuming that the vectors are the size that you really do want them to be
    > then the proper assignment is...


    unfortunately this is not true, the problem was just that I forgot to
    change the length in vectorB declaration, so this led me to the problem.
    Being just a warning (maybe), mixed up in several other meaningless
    warning, didn't really catch my attention, that's why I was wondering if
    it exists a conversion function which give you error when length are not
    the same (as conv_unsigned in the std_logic_arith library) when
    converting from a std_logic_vector to unsigned.
    Maybe is an issue for the Synplify compiler...

    >
    > vectorA <= ieee.numeric_std.resize(unsigned(vectorB), vectorA'length);
    > or
    > vectorA <= resize(unsigned(vectorB), vectorA'length);
    > if you've already got a "use ieee.numeric_std.all" statement in your code.
    >


    that's good to know, I've never used the function "resize". Thanks

    > KJ
    >
    >


    --
    Alessandro Basili
    CERN, PH/UGC
    Hardware Designer
     
    Al, Nov 8, 2006
    #4
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