structure alignment

[junky_fellow]

Hi,

I read some notes that say that if we keep the frequently accessed
structures aligned to the size of cpu cache line, then we may get
improved performance.

Is anyone aware of how this alignment can help in increasing the
performance ?

thanks for any help ....

 

[Thad Smith]

I read some notes that say that if we keep the frequently accessed
structures aligned to the size of cpu cache line, then we may get
improved performance.

Is anyone aware of how this alignment can help in increasing the
performance ?

Standard C says nothing about cache lines.

<OT> If a structure is aligned to the cache word size, it is contained in
the least number of cache words if the architecture uses cache memory. If
not aligned, it may be split split over an additional cache word. For
example, a structure 16 bytes long would be stored in two 8-byte cache
words if aligned or three 8-byte words if not aligned (an 8-byte word is an
example -- I don't know how it compares with typical computers). Fewer
words used means fewer main store fetches, with associated delay, to access
the entire structure.

Some compilers have options or pragmas to control alignment.
</OT>

 

[Mark McIntyre]

Hi,

I read some notes that say that if we keep the frequently accessed
structures aligned to the size of cpu cache line, then we may get
improved performance.

Is anyone aware of how this alignment can help in increasing the
performance ?

The ISO standard doesn't concern itself with implementation details like
this. you need to ask in a group where your OS, Hardware and compiler
are topical

<OT>
if your compioler doesnt automatically do this stuff, you need a new
compiler. Check its documentation
</ot>

 

[Chris Torek]

I read some notes that say that if we keep the frequently accessed
structures aligned to the size of cpu cache line, then we may get
improved performance.

It is also possible that this will make performance *worse*
(due to "bad" cache aliasing). It all depends on the design
of the cache and the actual access patterns.

Is anyone aware of how this alignment can help in increasing the
performance?

Cache design issues can occupy much of a college-course semester.
The basics are not that hard, but actual performance depends
critically on things well beyond the basics. So your best bet is
to get a good book on computer architecture.

To find out what effect alignment has on your particular problem
as run on your particular system, the only general-purpose answer
is to measure it. Note that apparently irrelevant system changes,
such as expanding main (non-cache) memory, can have odd effects
like making your code run *slower*, so these are very much "my
problem on my system as it exists at this very moment" measurements.
Generalizing is difficult.

See, e.g., <http://www.e-articles.info/e/a/title/What-is-CAS-latency/>,
and all of chapter 5 at <http://www.csee.umbc.edu/~plusquel/611/index.html>.

 

[Richard Tobin]

I read some notes that say that if we keep the frequently accessed
structures aligned to the size of cpu cache line, then we may get
improved performance.

Is anyone aware of how this alignment can help in increasing the
performance ?

[/QUOTE]

The ISO standard doesn't concern itself with implementation details like
this. you need to ask in a group where your OS, Hardware and compiler
are topical

It's not a question about a particular OS, hardware or compiler.

comp.arch might be a suitable group.

-- Richard
]