Stumped in Simulation Land

Discussion in 'VHDL' started by Shannon, Jul 29, 2009.

  1. Shannon

    Shannon Guest

    OK, this could NOT be more simple. Here is my code. A simple
    counter:

    rep_rate : process(system_clock, Reset)
    begin
    if (Reset = '1') then
    RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
    elsif rising_edge(system_clock) then
    Itrig <= '0';
    if (RepRate_Count < to_unsigned
    (SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
    RepRate_Count <= RepRate_Count + RepRate;
    else
    RepRate_Count <= RepRate;
    Itrig <= '1';
    end if;
    end if;
    end process;

    trig_out <= Itrig;

    This should produce single clock-wide pulses separated by 1/RepRate.
    ModelSim however shows in gate simulation that the Itrig pulses are
    LESS than one SYSTEM_FREQUENCY period long. How is this
    possible????? SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
    time is 3.773ns. I don't get it. The pulse separation is spot on.

    Shannon
     
    Shannon, Jul 29, 2009
    #1
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  2. Shannon

    Andy Guest

    On Jul 29, 11:07 am, Shannon <> wrote:
    > OK, this could NOT be more simple.  Here is my code.  A simple
    > counter:
    >
    > rep_rate : process(system_clock, Reset)
    > begin
    >         if (Reset = '1') then
    >                         RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
    >         elsif rising_edge(system_clock) then
    >                 Itrig <= '0';
    >                 if (RepRate_Count < to_unsigned
    > (SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
    >                         RepRate_Count <= RepRate_Count + RepRate;
    >                 else
    >                         RepRate_Count <= RepRate;
    >                         Itrig <= '1';
    >                 end if;
    >         end if;
    > end process;
    >
    > trig_out <= Itrig;
    >
    > This should produce single clock-wide pulses separated by 1/RepRate.
    > ModelSim however shows in gate simulation that the Itrig pulses are
    > LESS than one SYSTEM_FREQUENCY period long.  How is this
    > possible?????  SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
    > time is 3.773ns.  I don't get it.  The pulse separation is spot on.
    >
    > Shannon


    Gate simulation could be showing faster falling delay than rising
    delay on the signal driver. Especially since your separation is spot
    on. Check your clock to signal rise/fall times and you'll see what I'm
    talking about.

    Andy
     
    Andy, Jul 29, 2009
    #2
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  3. Shannon wrote:
    > OK, this could NOT be more simple. Here is my code. A simple
    > counter:
    >
    > rep_rate : process(system_clock, Reset)
    > begin
    > if (Reset = '1') then
    > RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
    > elsif rising_edge(system_clock) then
    > Itrig <= '0';
    > if (RepRate_Count < to_unsigned
    > (SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
    > RepRate_Count <= RepRate_Count + RepRate;
    > else
    > RepRate_Count <= RepRate;
    > Itrig <= '1';
    > end if;


    trig_out <= Itrig;

    > end if;
    > end process;
    >

    -- trig_out <= Itrig;
     
    Mike Treseler, Jul 29, 2009
    #3
  4. Shannon

    Shannon Guest

    On Jul 29, 10:16 am, Andy <> wrote:
    > On Jul 29, 11:07 am, Shannon <> wrote:
    >
    >
    >
    > > OK, this could NOT be more simple.  Here is my code.  A simple
    > > counter:

    >
    > > rep_rate : process(system_clock, Reset)
    > > begin
    > >         if (Reset = '1') then
    > >                         RepRate_Count <= to_unsigned(0,RepRate_Count'LENGTH);
    > >         elsif rising_edge(system_clock) then
    > >                 Itrig <= '0';
    > >                 if (RepRate_Count < to_unsigned
    > > (SYSTEM_FREQUENCY,RepRate_Count'LENGTH)) then
    > >                         RepRate_Count <= RepRate_Count + RepRate;
    > >                 else
    > >                         RepRate_Count <= RepRate;
    > >                         Itrig <= '1';
    > >                 end if;
    > >         end if;
    > > end process;

    >
    > > trig_out <= Itrig;

    >
    > > This should produce single clock-wide pulses separated by 1/RepRate.
    > > ModelSim however shows in gate simulation that the Itrig pulses are
    > > LESS than one SYSTEM_FREQUENCY period long.  How is this
    > > possible?????  SYSTEM_FREQUENCY is 250MHz (T= 4ns) and trig_out high
    > > time is 3.773ns.  I don't get it.  The pulse separation is spot on.

    >
    > > Shannon

    >
    > Gate simulation could be showing faster falling delay than rising
    > delay on the signal driver. Especially since your separation is spot
    > on. Check your clock to signal rise/fall times and you'll see what I'm
    > talking about.
    >
    > Andy


    Bingo Andy! You nailed it. The difference between the rising delay
    and falling delay is exactly 227ps. Very interesting. So since I
    learned something new today can I take the rest of the day off?

    Shannon
     
    Shannon, Jul 29, 2009
    #4
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