SV assertions workshop in San Jose , 20th June

Discussion in 'VHDL' started by SVTII, Jun 16, 2008.

  1. SVTII

    SVTII Guest

    SystemVerilog Assertions (SVA) are a feature of SystemVerilog which
    allows sophisticated, multi-cycle functional checks to be embedded in
    Verilog code as a powerful aid to design and verification. Course
    explains the advantages of Assertion Based Design and Verification
    using SystemVerilog Assertions (SVA). This course describes in detail
    the structure of a SVA and demonstrates, with realistic examples, the
    full range of language features. Course has good balance between hands-
    on Lab and Lecture.
    This course is intended for RTL design engineers and verification
    engineers who need to become skilled in property writing.

    For details contact SVTII or check the below link

    http://www.svtii.com/files/System-Verilog-Assertions-SVTI.pdf
     
    SVTII, Jun 16, 2008
    #1
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