Synthesis Error in XST

Discussion in 'VHDL' started by Nisheeth, Mar 21, 2005.

  1. Nisheeth

    Nisheeth Guest

    hello group
    I have been using Xilinx ISE + Modelsim for last 2
    months.During this time i made small projects and did simulation. I
    tried to carry out next logical step after simulation this
    time..translate,map,P&R.
    Though the following code compiled w/o error and simulation was ok but
    gave error in translate step.

    Code
    ---

    entity result_out is
    port (
    pe_row : in std_logic_vector(7 downto 0);
    ws_row : in std_logic_vector(7 downto 0);
    clock : in std_logic;
    pe_moving_row: out std_logic_vecotr(7 downto 0)
    );
    end entity;

    architecture behavioural of result_out is
    begin
    process(clock,pe_row,ws_row)
    begin
    if clock='1' and clock'event then
    pe_moving_row<=pe_row + ws_row;
    else
    pe_moving_row<=(others=>'Z');
    end if;
    end process;
    end architecture;

    -----

    Error-> Signal pe_moving_row cannot be synthesized, bad synchronous
    description.

    After hit and trial i found removing clock'event makes the thing
    work...but i have no clue why....can anyonet tell me why ?

    A bit info about how this block will be used...
    16 "result_out" blocks will be connected in parallel and at a time
    only 1 "result_out" will output data on "pe_moving_row"
    bus...depending on to which block clock is supplied...

    Regards
    Nisheeth
     
    Nisheeth, Mar 21, 2005
    #1
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  2. Nisheeth

    Tim Good Guest

    Hi,

    Your sample VHDL is asking the synthesis tool to create logic which does
    the following:

    ONLY at the instant of a positive edge transition of the clock (and for
    only this instant) set the output pe_moving_row to the addition of
    pe_row and ws_row and for all remaining time set it to be tristate.
    This is simply not possible!

    If you are trying to add the two numbers together then this is purely
    combinational and you dont need a process block:

    architecture RTL of result_out is
    begin
    pe_moving_row<=pe_row + ws_row;
    end RTL;

    If you are asking for something with a tri-state output then you will
    need an extra signal, "OutputEnable". Note to infer latch behavior the
    "clock if statement" does not have an else :


    architecture RTL of result_out is
    process(clock,pe_row,ws_row,output_enable)
    begin
    if clock='1' and clock'event then
    if output_enable = '1' then
    pe_moving_row<=pe_row + ws_row;
    else
    pe_moving_row<=(others=>'Z');
    end if;
    end if;
    end process;
    end architecture;

    Hope this helps,

    Tim


    Nisheeth wrote:
    > hello group
    > I have been using Xilinx ISE + Modelsim for last 2
    > months.During this time i made small projects and did simulation. I
    > tried to carry out next logical step after simulation this
    > time..translate,map,P&R.
    > Though the following code compiled w/o error and simulation was ok but
    > gave error in translate step.
    >
    > Code
    > ---
    >
    > entity result_out is
    > port (
    > pe_row : in std_logic_vector(7 downto 0);
    > ws_row : in std_logic_vector(7 downto 0);
    > clock : in std_logic;
    > pe_moving_row: out std_logic_vecotr(7 downto 0)
    > );
    > end entity;
    >
    > architecture behavioural of result_out is
    > begin
    > process(clock,pe_row,ws_row)
    > begin
    > if clock='1' and clock'event then
    > pe_moving_row<=pe_row + ws_row;
    > else
    > pe_moving_row<=(others=>'Z');
    > end if;
    > end process;
    > end architecture;
    >
    > -----
    >
    > Error-> Signal pe_moving_row cannot be synthesized, bad synchronous
    > description.
    >
    > After hit and trial i found removing clock'event makes the thing
    > work...but i have no clue why....can anyonet tell me why ?
    >
    > A bit info about how this block will be used...
    > 16 "result_out" blocks will be connected in parallel and at a time
    > only 1 "result_out" will output data on "pe_moving_row"
    > bus...depending on to which block clock is supplied...
    >
    > Regards
    > Nisheeth
     
    Tim Good, Mar 21, 2005
    #2
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  3. Nisheeth

    Nisheeth Guest

    hi tim
    thanks ...i believe i understood the mistake i m making.


    nisheeth
     
    Nisheeth, Mar 22, 2005
    #3
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