type conversation problems

[Olaf Petzold]

Hi,

I've read some google urls concerning type conversation and I'm
confused. IEEE does have it's own libraries, synopsis libs starts with
ieee, both have 'std' in there paths .... Synopsis libs should not be
used, even they are used on the same web page. std_logic_vector should
be use, a lot of books are using bit_vector ... synopsis should not
used for enw designs, well.

Does exist a generell rule/guidelines for using libs or an url for this?

Well, now to my problem:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.ext;

use std.textio.all;
use work.image_pkg.all;

architecture fsm_full of sample_ram is

component ram_512x80 is
generic (
RESET_ACTIVE : std_logic);
port (
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
AB : in std_logic_vector(8 downto 0);
DB_I : in std_logic_vector(79 downto 0);
DB_O : out std_logic_vector(79 downto 0);
we : in std_logic);
end component ram_512x80;

constant TOP_RAM_ADDR : natural := 512; -- conform to ram 512*x !!
subtype addrbus_t is integer range 0 to TOP_RAM_ADDR-1;

type ram_bus_t is record
addr : addrbus_t;
...
end record;
signal ram : ram_bus_t;

...

begin

-- fsm and address calculations
...

ram_512x80_i : ram_512x80
generic map (
RESET_ACTIVE => RESET_ACTIVE)
port map (
...
AB => to_stdlogicvector(ram.addr, 9) -- line 700
);

...


log_proc_txt : process is
variable L : line;
file F : text open write_mode is "mem_write.txt";
begin
wait until rising_edge(clk) and (ram.en = '1' and ram.we = '1');
write(L, string'("0x") & heximage(ram.addr) -- line 747
& string'(": 0x") & heximage(ram.di));
writeline(F, L);
end process;

which got the compiler errors:

** Error: (700): No feasible entries for subprogram "to_stdlogicvector".
** Error: (700): The actual for formal 'ab' is not
a globally static expression.
** Error: (747): No feasible entries for subprogram
"heximage".
** Error: (748): Bad expression.
** Error: (748): Bad expression.
** Error: (747): No feasible entries for subprogram
"write".

based on the same wrong conversation. It doesn't matter if I use
natural range A to B, or integer range A to B

How can I convert this?

Thanks
Olaf

 

[jens]

Using std_logic_arith is supposedly not a good idea, especially when
used with numeric_std, so use just numeric_std.

SLV to/from integer conversions:

integer_signal <= to_integer(signed(slv_signal))
integer_signal <= to_integer(unsigned(slv_signal))
slv_signal <= std_logic_vector(to_signed(integer_signal,<# of bits>)
slv_signal <= std_logic_vector(to_unsigned(integer_signal,<# of bits>)

 

[Ajeetha]

Hi,
Try:

AB => std_logic_vector(to_unsigned(ram.addr, 9)); -- line 700

Read FAQ @ http://www.vhdl.org/comp.lang.vhdl - this is discussed in
great length - I've it handy all the time.

HTH
Ajeetha
www.noveldv.com