Type of actual ports is not compatible with type of ports of entity.

Discussion in 'VHDL' started by mreister, May 25, 2010.

  1. mreister

    mreister

    Joined:
    Aug 19, 2008
    Messages:
    10
    I have a realy anoying error on my hands. I think I understand what its trying to tell me but, I cant seem to find the mismatch. As I understand it the error, which apears in the title of this post, is telling my that the actual signal that I am assigning to the entity of uart_tx is a diffrent type than the actual port declaration. If this is so I should be able to find where I am assigning the wrong data type and that should be that. But here is the relavent code:
    Top module:
    entity uart is
    generic(
    -- Default setting:
    -- 19200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
    DBIT: integer := 8; -- # data bits
    SB_TICK: integer :=16; -- # ticks for stop bits , 16/24/32
    -- # for 1/1.5/2 stop bits
    DVSR: integer := 163; -- # baud rate divisor
    -- # DVSR = 50M/(16*baud rate)
    DVSR_BIT: integer := 8; -- # bits of DVSR
    FIFO_W: integer := 2 -- # addr bits of FIFO
    -- # words in FIFO=2^FIFO_W
    );
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    rd_uart : in STD_LOGIC;
    wr_uart : in STD_LOGIC;
    rx : in STD_LOGIC;
    w_data : in STD_LOGIC_VECTOR (7 downto 0);
    tx_full : out STD_LOGIC;
    rx_empty : out STD_LOGIC;
    r_data : out STD_LOGIC_VECTOR (7 downto 0);
    tx : out STD_LOGIC);
    end uart;

    architecture str_arch of uart is
    signal tick: STD_LOGIC;
    signal rx_done_tick: STD_LOGIC;
    signal tx_fifo_out: STD_LOGIC_VECTOR(7 downto 0);
    signal rx_data_out: STD_LOGIC_VECTOR(7 downto 0);
    signal tx_empty, tx_fifo_not_empty: STD_LOGIC;
    signal tx_done_tick: STD_LOGIC;

    begin
    uart_tx_unit: entity work.uart_tx(arch)
    generic map(DBIT=>DBIT,SB_TICK=>SB_TICK)
    port map(clk=clk,
    reset=>reset,
    tx_start=>tx_fifo_not_empty,
    s_tick=>tick,
    din=>tx_fifo_out,
    tx_done_tick=> tx_done_tick,
    tx=> tx);
    end str_arch;

    -- the entity in question

    entity uart_tx is
    generic(
    DBIT: integer := 8;
    SB_TICK: integer := 16
    );
    Port ( clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    tx_start : in STD_LOGIC;
    s_tick : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR (7 downto 0);
    tx_done_tick : out STD_LOGIC;
    tx : out STD_LOGIC);
    end uart_tx;

    architecture arch of uart_tx is
    type state_type is (idle, start, data, stop);
    signal state_reg, state_next: state_type;
    signal s_reg, s_next: unsigned(3 downto 0);
    signal n_reg, n_next: unsigned(2 downto 0);
    signal b_reg, b_next: std_logic_vector(7 downto 0);
    signal tx_reg, tx_next: std_logic;
    begin
    end arch;


    ---- I didn't include the behavior of the uart_tx because i didn't think it was relivent to the question. I checked for a type mismatch a bunch of times but I cant find it.... Any suggestions?
    mreister, May 25, 2010
    #1
    1. Advertising

  2. mreister

    mreister

    Joined:
    Aug 19, 2008
    Messages:
    10
    Nevermind solved

    I forgot the include a '>' in one of the portmap declaration..... didn't seem to be a very accurate error message
    mreister, May 25, 2010
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Samuel van Laere

    Entity Name or Entity Number?

    Samuel van Laere, Feb 24, 2007, in forum: HTML
    Replies:
    4
    Views:
    1,615
    Jukka K. Korpela
    Feb 24, 2007
  2. markla
    Replies:
    1
    Views:
    540
    Steven Cheng
    Oct 6, 2008
  3. Norm
    Replies:
    3
    Views:
    2,698
  4. ThatsIT.net.au

    Entity, problem with entity key

    ThatsIT.net.au, Sep 6, 2009, in forum: ASP .Net
    Replies:
    1
    Views:
    1,190
    ThatsIT.net.au
    Sep 7, 2009
  5. pantagruel
    Replies:
    0
    Views:
    236
    pantagruel
    Feb 17, 2006
Loading...

Share This Page