Unconstrained ports for synthesis

Discussion in 'VHDL' started by Mohammed A khader, Apr 20, 2005.

  1. Hi all,

    I am having a component Multiplier with unconstrained ports. But this
    is not my top_level_entity and ports are implicity constrained while
    instanciating this component.

    It simulates well but while synthezing Quartus says that ports must be
    constrained. I think that Quartus could infer it from instanciation
    syntax. Is there any solution to get around it

    Thanks.

    -- Mohammed A Khader.
    Mohammed A khader, Apr 20, 2005
    #1
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  2. Hello,

    Can you be more specific as to the exact message that Quartus gives? You
    can cut ans paste the Quartus message in the reply. Also can you describe
    what is meant by "implictly constrainedwhile instanciating" in the post?

    Subroto Datta
    Altera Corp.

    "Mohammed A khader" <> wrote in message
    news:...
    > Hi all,
    >
    > I am having a component Multiplier with unconstrained ports. But this
    > is not my top_level_entity and ports are implicity constrained while
    > instanciating this component.
    >
    > It simulates well but while synthezing Quartus says that ports must be
    > constrained. I think that Quartus could infer it from instanciation
    > syntax. Is there any solution to get around it
    >
    > Thanks.
    >
    > -- Mohammed A Khader.
    >
    Subroto Datta, Apr 20, 2005
    #2
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  3. Hi,

    -- Error messages are......

    Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
    ports must be constrained
    Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(27): ports
    must be constrained
    Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(28): ports
    must be constrained
    Error: Can't elaborate user hierarchy
    "Core:Core_Map|Datapath:Datapath_Map"
    Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0
    warnings
    Error: Processing ended: Wed Apr 20 16:33:52 2005
    Error: Elapsed time: 00:00:05

    -- My Multiplier component is .........
    entity Multiplier_Synth is
    port(
    Op1 : in signed; -- Operator 1
    Op2 : in signed; -- Operator 2
    Mult_Out : out signed -- Multiplication Result
    );
    end entity Multiplier_Synth;

    architecture Multiplier_Synth_Arch of Multiplier_Synth is
    begin
    Mult_Out <= Op1 * Op2;
    end architecture Multiplier_Synth_Arch;

    -- And it has been instantiated in an entity called Datapath_Map as
    .......

    signal Mux1_Out : WORD20; -- Output of Mux1
    signal Mux2_Out : WORD; -- Output of Mux2
    signal Mult_Out : signed(39 downto 0); -- Multiplier Output

    Multiplier_Map : entity work.Multiplier_Synth(Multiplier_Synth_Arch)
    port map(
    Op1 => Mux1_Out,
    Op2 => Mux2_Out,
    Mult_Out => Mult_Out
    );

    Mux1_Out , Mux2_Out and Mult_Out are constrained signals . Hence
    Op1,Op2,Mult_Out implicitly can be constrained by bit length of
    20,20,40 respectively.

    Thanks..

    -- Mohammed A Khader.
    Mohammed A Khader, Apr 20, 2005
    #3
  4. Mohammed A Khader wrote:

    > Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
    > ports must be constrained


    > -- My Multiplier component is .........
    > entity Multiplier_Synth is
    > port(
    > Op1 : in signed; -- Operator 1
    > Op2 : in signed; -- Operator 2
    > Mult_Out : out signed -- Multiplication Result
    > );
    > end entity Multiplier_Synth;


    Use generic parameters - e.g.:


    entity Multiplier_Synth is
    generic(
    width : integer:=16 );
    port(
    Op1 : in signed(width-1 downto 0);
    Op2 : in signed(width-1 downto 0);
    Mult_Out : out signed(width*2-1 downto 0)
    );
    end entity Multiplier_Synth;


    Generic parameters are overridden, if a generic mapping is used during
    instantiation. (Otherwise the given default value is used.)
    Because you have to define the bitwidth somewhere in your design, it
    does not matter where and how. Therefore Generic paramters are suitable.
    You can feed them from the very bottom to the top entity.

    Ralf
    Ralf Hildebrandt, Apr 20, 2005
    #4
  5. Hello Mohammed,

    We will be adding support for unconstrained entity ports in 5.1,
    due out later this year (we need to get 5.0 out first :)). In the
    interim please use the generic approach suggested by Ralf.

    Hope this helps,
    Subroto Datta
    Altera Corp.
    Subroto Datta, Apr 21, 2005
    #5
  6. Mohammed  A khader

    Ray Andraka Guest

    Mohammed A khader wrote:

    > Hi all,
    >
    > I am having a component Multiplier with unconstrained ports. But this
    >is not my top_level_entity and ports are implicity constrained while
    >instanciating this component.
    >
    > It simulates well but while synthezing Quartus says that ports must be
    >constrained. I think that Quartus could infer it from instanciation
    >syntax. Is there any solution to get around it
    >
    >Thanks.
    >
    >-- Mohammed A Khader.
    >
    >
    >

    I do not believe the Quartus compiler supports unconstrained ports.
    Either use generics to size the port, or use a synthesizer such as
    synplify that does support unconstrained ports.

    --
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950
    email
    http://www.andraka.com

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
    Ray Andraka, Apr 22, 2005
    #6
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