Unit testing vhdl using xUnit?

Discussion in 'VHDL' started by pontus.stenstrom@gmail.com, Jan 15, 2008.

  1. Guest

    When I talk to my software colleagues, they often use words like jUnit
    or xUnit to describe their
    test/verification setup. Is this a useful concept for vhdl designs?

    I understand that there are tools which can gather test statistics
    etc. if the testing is done
    according to some patterns, and deliver test results in a suitable
    (xml?) format.

    Any hints or tips would be appreciated.

    Pontus

    (I currently *do* test my designs with testbenches, mostly directed
    tests, using vhdl assertions and
    some psl. I end up with a long text output which I grep for warnings/
    errors. No warnings - no problems;)
     
    , Jan 15, 2008
    #1
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  2. I think you are a little unclear about jUnit and xUnit are.

    jUnit is the name of a framework for writing java tests.
    xUnit is the growth of that framework to include other languages.

    These too proper names do not write any tests for you. They provide a
    template to write your tests. If you follow the template,then execution of
    the tests and gathering the results are automatic.

    Is this useful for vhdl? Cadence believes so, they have product called
    Incisive Enterprise Manager. It provides a frame work for RTL design
    tests. If you follow thier rules/templates. you get the same benefits of
    using xUnit. The difference is money. xUnit is a free framework that does
    not cover the RTL design flow.

    Is it useful to create an open source framework for RTL design testing?
    If you have free time. knock yourself out. All of the EDA companies are
    turning out products. The smaller companies would love anything that gives
    them benefits for free.

    All these frameworks will not change eliminate what you do now. you will
    still have to use testbenches/assertions for testing. You would have to
    modify you tests to match the framwork guidelines. From there you can run
    the tests and collect the results. All the bells and whistles.




    <> wrote in message
    news:...
    > When I talk to my software colleagues, they often use words like jUnit
    > or xUnit to describe their
    > test/verification setup. Is this a useful concept for vhdl designs?
    >
    > I understand that there are tools which can gather test statistics
    > etc. if the testing is done
    > according to some patterns, and deliver test results in a suitable
    > (xml?) format.
    >
    > Any hints or tips would be appreciated.
    >
    > Pontus
    >
    > (I currently *do* test my designs with testbenches, mostly directed
    > tests, using vhdl assertions and
    > some psl. I end up with a long text output which I grep for warnings/
    > errors. No warnings - no problems;)
     
    Dwayne Dilbeck, Jan 15, 2008
    #2
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  3. I agree with the need for such an extension within an VHDL editor. It is
    pretty handy to get a testbench generated. Saves lots of boring work.
    What I would like to see within an editor would do a similar job as in
    http://www.vhdl-online.de/TB-GEN/
    If the eclipse project SIGN would include such, that could be a handy
    editor. Using any other simulation tool afterwords for simulation of
    course. A command line tool is another possibility.


    Heinz


    Dwayne Dilbeck schrieb:
    > I think you are a little unclear about jUnit and xUnit are.
    >
    > jUnit is the name of a framework for writing java tests.
    > xUnit is the growth of that framework to include other languages.
    >
    > These too proper names do not write any tests for you. They provide a
    > template to write your tests. If you follow the template,then execution of
    > the tests and gathering the results are automatic.
    >
    > Is this useful for vhdl? Cadence believes so, they have product called
    > Incisive Enterprise Manager. It provides a frame work for RTL design
    > tests. If you follow thier rules/templates. you get the same benefits of
    > using xUnit. The difference is money. xUnit is a free framework that does
    > not cover the RTL design flow.
    >
    > Is it useful to create an open source framework for RTL design testing?
    > If you have free time. knock yourself out. All of the EDA companies are
    > turning out products. The smaller companies would love anything that gives
    > them benefits for free.
    >
    > All these frameworks will not change eliminate what you do now. you will
    > still have to use testbenches/assertions for testing. You would have to
    > modify you tests to match the framwork guidelines. From there you can run
    > the tests and collect the results. All the bells and whistles.
    >
    >
    >
    >
    > <> wrote in message
    > news:...
    >> When I talk to my software colleagues, they often use words like jUnit
    >> or xUnit to describe their
    >> test/verification setup. Is this a useful concept for vhdl designs?
    >>
    >> I understand that there are tools which can gather test statistics
    >> etc. if the testing is done
    >> according to some patterns, and deliver test results in a suitable
    >> (xml?) format.
    >>
    >> Any hints or tips would be appreciated.
    >>
    >> Pontus
    >>
    >> (I currently *do* test my designs with testbenches, mostly directed
    >> tests, using vhdl assertions and
    >> some psl. I end up with a long text output which I grep for warnings/
    >> errors. No warnings - no problems;)

    >
    >
     
    Heinz Haeberle, Mar 11, 2008
    #3
  4. Heinz Haeberle <> writes:

    > I agree with the need for such an extension within an VHDL editor. It
    > is pretty handy to get a testbench generated. Saves lots of boring
    > work.
    > What I would like to see within an editor would do a similar job as in
    > http://www.vhdl-online.de/TB-GEN/
    > If the eclipse project SIGN would include such, that could be a handy
    > editor. Using any other simulation tool afterwords for simulation of
    > course. A command line tool is another possibility.


    Does Emacs VHDL-mode do what you want?

    It interprets an entity declaration and you can then "paste" it as an
    instantiation, some signals, constants (for the generics), or it will
    even create an entire testbench for you, with your DUT instantiated,
    wired up, with a clock ready running and a process which says
    "-- insert your stimulus here". Obviously, it can;t do the last part
    for you ;-)

    It's also customisable, so I've modified mine to add a "finished"
    signal, which is set at the end of the stimulus procedure. This
    signal is used to stop the clock, so all my sims terminate
    automatically when complete, which makes automated runs easier.

    Cheers,
    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.net/electronics.html
     
    Martin Thompson, Mar 12, 2008
    #4
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