Unknown bug in program

L

Leow Yuan Yeow

Hi, I have a strange problem in the attached program iir-3t.vhd, which I
am unable to figure out. The problem is that a particular 32-bit integer
register is assigned a constant value of 1 for post-place-and-route
simulation and also on my RC100 board(stuck in infinite loop with no
output because of it). However, the register output correctly in
behavioral simulation. The code snippet having the error is:

when T2_S19 =>
TMP_T59 <= 3 * R0_F0_incr(THREAD_NUM);
T2_STATE <= T2_S20;

when T2_S20 =>
TMP_T60 <= k_priv(THREAD_NUM) + TMP_T59;
T2_STATE <= T2_S21;

when T2_S21 =>
k_priv(THREAD_NUM) <= TMP_T60;
T2_STATE <= T2_S9;

In the PPAR simulation, TMP_T59 has a constant value of 3, which is
correct. However, the value of TMP_T60 and k_priv(THREAD_NUM)
(THREAD_NUM is a constant in each process) which are integers, have its
value stuck at 1 even though the same code is executed past many times.
TMP_60 is never assigned anywhere else, and this problem does not occur
in simulation (i.e. the value of TMP_60 and k_priv actually gets
incremented).

Any help to see where the problem lies is deeply appreciated!


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;

library work;
use work.type_const_pkg.all;

entity main is
port (
CLK : IN std_logic ;
RST : IN std_logic ;
T0_MAN_RST: IN std_logic;
START : IN std_logic ;
DONE : OUT std_logic;
OUTPUT: OUT integer
);end main;

architecture rtl of main is

CONSTANT T0_FINAL_STATE: natural := 82;
CONSTANT T0_S0: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001";
CONSTANT T0_S1: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010";
CONSTANT T0_S2: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100";
CONSTANT T0_S3: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000";
CONSTANT T0_S4: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000";
CONSTANT T0_S5: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000";
CONSTANT T0_S6: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000";
CONSTANT T0_S7: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000";
CONSTANT T0_S8: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000";
CONSTANT T0_S9: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000";
CONSTANT T0_S10: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000";
CONSTANT T0_S11: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000";
CONSTANT T0_S12: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000";
CONSTANT T0_S13: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000";
CONSTANT T0_S14: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000";
CONSTANT T0_S15: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000";
CONSTANT T0_S16: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000";
CONSTANT T0_S17: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000";
CONSTANT T0_S18: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000";
CONSTANT T0_S19: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000";
CONSTANT T0_S20: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000";
CONSTANT T0_S21: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000";
CONSTANT T0_S22: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000";
CONSTANT T0_S23: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000";
CONSTANT T0_S24: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000";
CONSTANT T0_S25: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000";
CONSTANT T0_S26: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000";
CONSTANT T0_S27: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000";
CONSTANT T0_S28: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000";
CONSTANT T0_S29: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000";
CONSTANT T0_S30: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000";
CONSTANT T0_S31: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000";
CONSTANT T0_S32: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000";
CONSTANT T0_S33: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000";
CONSTANT T0_S34: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000";
CONSTANT T0_S35: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000";
CONSTANT T0_S36: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000";
CONSTANT T0_S37: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000";
CONSTANT T0_S38: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000";
CONSTANT T0_S39: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000";
CONSTANT T0_S40: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000";
CONSTANT T0_S41: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000";
CONSTANT T0_S42: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000";
CONSTANT T0_S43: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000";
CONSTANT T0_S44: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000";
CONSTANT T0_S45: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000";
CONSTANT T0_S46: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000";
CONSTANT T0_S47: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000";
CONSTANT T0_S48: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000";
CONSTANT T0_S49: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000";
CONSTANT T0_S50: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000";
CONSTANT T0_S51: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000";
CONSTANT T0_S52: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000";
CONSTANT T0_S53: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000";
CONSTANT T0_S54: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S55: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S56: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S57: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S58: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S59: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S60: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S61: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S62: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S63: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S64: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S65: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S66: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S67: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S68: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S69: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S70: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S71: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S72: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S73: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S74: std_logic_vector(T0_FINAL_STATE downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S75: std_logic_vector(T0_FINAL_STATE downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S76: std_logic_vector(T0_FINAL_STATE downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S77: std_logic_vector(T0_FINAL_STATE downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S78: std_logic_vector(T0_FINAL_STATE downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S79: std_logic_vector(T0_FINAL_STATE downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S80: std_logic_vector(T0_FINAL_STATE downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S81: std_logic_vector(T0_FINAL_STATE downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T0_S82: std_logic_vector(T0_FINAL_STATE downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000";
signal T0_STATE: std_logic_vector(T0_FINAL_STATE downto 0);

CONSTANT T1_FINAL_STATE: natural := 72;
CONSTANT T1_S0: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001";
CONSTANT T1_S1: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010";
CONSTANT T1_S2: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100";
CONSTANT T1_S3: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000";
CONSTANT T1_S4: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000";
CONSTANT T1_S5: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000";
CONSTANT T1_S6: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000";
CONSTANT T1_S7: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000";
CONSTANT T1_S8: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000";
CONSTANT T1_S9: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000";
CONSTANT T1_S10: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000";
CONSTANT T1_S11: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000";
CONSTANT T1_S12: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000";
CONSTANT T1_S13: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000";
CONSTANT T1_S14: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000";
CONSTANT T1_S15: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000";
CONSTANT T1_S16: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000";
CONSTANT T1_S17: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000";
CONSTANT T1_S18: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000";
CONSTANT T1_S19: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000";
CONSTANT T1_S20: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000";
CONSTANT T1_S21: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000";
CONSTANT T1_S22: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000";
CONSTANT T1_S23: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000";
CONSTANT T1_S24: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000";
CONSTANT T1_S25: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000";
CONSTANT T1_S26: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000";
CONSTANT T1_S27: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000";
CONSTANT T1_S28: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000";
CONSTANT T1_S29: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000";
CONSTANT T1_S30: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000";
CONSTANT T1_S31: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000";
CONSTANT T1_S32: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000";
CONSTANT T1_S33: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000";
CONSTANT T1_S34: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000";
CONSTANT T1_S35: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000";
CONSTANT T1_S36: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000";
CONSTANT T1_S37: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000";
CONSTANT T1_S38: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000";
CONSTANT T1_S39: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000";
CONSTANT T1_S40: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000";
CONSTANT T1_S41: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000";
CONSTANT T1_S42: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000";
CONSTANT T1_S43: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000";
CONSTANT T1_S44: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000";
CONSTANT T1_S45: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000";
CONSTANT T1_S46: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000";
CONSTANT T1_S47: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000";
CONSTANT T1_S48: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000";
CONSTANT T1_S49: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000";
CONSTANT T1_S50: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000";
CONSTANT T1_S51: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000";
CONSTANT T1_S52: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000";
CONSTANT T1_S53: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000";
CONSTANT T1_S54: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S55: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S56: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S57: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S58: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S59: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S60: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S61: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S62: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S63: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S64: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S65: std_logic_vector(T1_FINAL_STATE downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S66: std_logic_vector(T1_FINAL_STATE downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S67: std_logic_vector(T1_FINAL_STATE downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S68: std_logic_vector(T1_FINAL_STATE downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S69: std_logic_vector(T1_FINAL_STATE downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S70: std_logic_vector(T1_FINAL_STATE downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S71: std_logic_vector(T1_FINAL_STATE downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T1_S72: std_logic_vector(T1_FINAL_STATE downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000";
signal T1_STATE: std_logic_vector(T1_FINAL_STATE downto 0);
signal T1_MAN_RST: std_logic;

CONSTANT T2_FINAL_STATE: natural := 72;
CONSTANT T2_S0: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001";
CONSTANT T2_S1: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010";
CONSTANT T2_S2: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100";
CONSTANT T2_S3: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000";
CONSTANT T2_S4: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000";
CONSTANT T2_S5: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000";
CONSTANT T2_S6: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000";
CONSTANT T2_S7: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000";
CONSTANT T2_S8: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000";
CONSTANT T2_S9: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000";
CONSTANT T2_S10: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000";
CONSTANT T2_S11: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000";
CONSTANT T2_S12: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000";
CONSTANT T2_S13: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000";
CONSTANT T2_S14: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000";
CONSTANT T2_S15: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000";
CONSTANT T2_S16: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000";
CONSTANT T2_S17: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000";
CONSTANT T2_S18: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000";
CONSTANT T2_S19: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000";
CONSTANT T2_S20: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000";
CONSTANT T2_S21: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000";
CONSTANT T2_S22: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000";
CONSTANT T2_S23: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000";
CONSTANT T2_S24: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000";
CONSTANT T2_S25: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000";
CONSTANT T2_S26: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000";
CONSTANT T2_S27: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000";
CONSTANT T2_S28: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000";
CONSTANT T2_S29: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000";
CONSTANT T2_S30: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000";
CONSTANT T2_S31: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000";
CONSTANT T2_S32: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000";
CONSTANT T2_S33: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000";
CONSTANT T2_S34: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000";
CONSTANT T2_S35: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000";
CONSTANT T2_S36: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000";
CONSTANT T2_S37: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000";
CONSTANT T2_S38: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000";
CONSTANT T2_S39: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000";
CONSTANT T2_S40: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000";
CONSTANT T2_S41: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000";
CONSTANT T2_S42: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000";
CONSTANT T2_S43: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000";
CONSTANT T2_S44: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000";
CONSTANT T2_S45: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000";
CONSTANT T2_S46: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000";
CONSTANT T2_S47: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000";
CONSTANT T2_S48: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000";
CONSTANT T2_S49: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000";
CONSTANT T2_S50: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000";
CONSTANT T2_S51: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000";
CONSTANT T2_S52: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000";
CONSTANT T2_S53: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000";
CONSTANT T2_S54: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S55: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S56: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S57: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S58: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S59: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S60: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S61: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S62: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S63: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S64: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S65: std_logic_vector(T2_FINAL_STATE downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S66: std_logic_vector(T2_FINAL_STATE downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S67: std_logic_vector(T2_FINAL_STATE downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S68: std_logic_vector(T2_FINAL_STATE downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S69: std_logic_vector(T2_FINAL_STATE downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S70: std_logic_vector(T2_FINAL_STATE downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S71: std_logic_vector(T2_FINAL_STATE downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000";
CONSTANT T2_S72: std_logic_vector(T2_FINAL_STATE downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000";
signal T2_STATE: std_logic_vector(T2_FINAL_STATE downto 0);
signal T2_MAN_RST: std_logic;


CONSTANT R0_NUM_THREADS: natural := 3;
CONSTANT R0_NUM_SYNCS: natural := 4;

subtype R0_sync_type is std_logic_vector(R0_NUM_THREADS-1 downto 0);
type R0_barrier_type is array(R0_NUM_SYNCS-1 downto 0) of R0_sync_type;
subtype R0_and_type is std_logic_vector(R0_NUM_SYNCS-1 downto 0);

signal R0_end_array: R0_barrier_type;
signal R0_start: std_logic;
signal R0_end_and: R0_and_type;

CONSTANT SHARED_FINAL_STATE: natural := 1;
CONSTANT SHARED_S0: std_logic_vector(SHARED_FINAL_STATE downto 0) := "01";
CONSTANT SHARED_S1: std_logic_vector(SHARED_FINAL_STATE downto 0) := "10";
signal delay2_STATE: std_logic_vector(SHARED_FINAL_STATE downto 0);
signal delay2_reqs: std_logic_vector(2 downto 0);
signal delay2_acks: std_logic_vector(2 downto 0);
signal input_sum_STATE: std_logic_vector(SHARED_FINAL_STATE downto 0);
signal input_sum_reqs: std_logic_vector(2 downto 0);
signal input_sum_acks: std_logic_vector(2 downto 0);
signal output_sum_STATE: std_logic_vector(SHARED_FINAL_STATE downto 0);
signal output_sum_reqs: std_logic_vector(2 downto 0);
signal output_sum_acks: std_logic_vector(2 downto 0);


signal order: integer;
signal coeffa: int_array_1d(0 to 17-1);
signal coeffb: int_array_1d(0 to 16-1);
signal delay: int_array_1d(0 to 17-1);
signal delay2: int_array_1d(0 to 17-1);
signal delay2_inputs: int_array_1d(0 to 3-1);
signal delay2_dim_1: int_array_1d(0 to 3-1);
signal input_sum: integer;
signal input_sum_inputs: int_array_1d(0 to 3-1);
signal output_sum: integer;
signal output_sum_inputs: int_array_1d(0 to 3-1);
signal i: integer;
signal i_priv: int_array_1d(0 to 3-1);
signal j: integer;
signal j_priv: int_array_1d(0 to 3-1);
signal k: integer;
signal k_priv: int_array_1d(0 to 3-1);
signal TMP_T0: integer;
signal TMP_T1: integer;
signal R0_F0_init: int_array_1d(0 to 3-1);
signal R0_F0_end: int_array_1d(0 to 3-1);
signal R0_F0_incr: int_array_1d(0 to 3-1);
signal R0_F1_init: int_array_1d(0 to 3-1);
signal R0_F1_end: int_array_1d(0 to 3-1);
signal R0_F1_incr: int_array_1d(0 to 3-1);
signal R0_F2_init: int_array_1d(0 to 3-1);
signal R0_F2_end: int_array_1d(0 to 3-1);
signal R0_F2_incr: int_array_1d(0 to 3-1);
signal TMP_T18: integer;
signal TMP_T19: integer;
signal TMP_T20: integer;
signal TMP_T21: integer;
signal TMP_T12: integer;
signal TMP_T22: integer;
signal TMP_T23: integer;
signal TMP_T24: integer;
signal TMP_T25: integer;
signal TMP_T26: integer;
signal TMP_T27: integer;
signal TMP_T28: integer;
signal TMP_T14: integer;
signal TMP_T29: integer;
signal TMP_T30: integer;
signal TMP_T31: integer;
signal TMP_T32: integer;
signal TMP_T33: integer;
signal TMP_T34: integer;
signal TMP_T35: integer;
signal TMP_T36: integer;
signal TMP_T16: integer;
signal TMP_T37: integer;
signal TMP_T38: integer;
signal TMP_T39: integer;
signal TMP_T109: integer;
signal TMP_T110: integer;
signal TMP_T111: integer;
signal TMP_T112: integer;
signal TMP_T113: integer;
signal TMP_T114: integer;
signal TMP_T115: integer;
signal TMP_T116: integer;
signal TMP_T117: integer;
signal TMP_T118: integer;
signal TMP_T119: integer;
signal TMP_T120: integer;
signal TMP_T121: integer;
signal TMP_T122: integer;
signal TMP_T123: integer;
signal TMP_T124: integer;
signal TMP_T125: integer;
signal TMP_T126: integer;
signal TMP_T127: integer;
signal TMP_T128: integer;
signal TMP_T129: integer;
signal TMP_T130: integer;
signal TMP_T131: integer;
signal TMP_T132: integer;
signal TMP_T133: integer;
signal TMP_T134: integer;
signal TMP_T135: integer;
signal TMP_T136: integer;
signal TMP_T137: integer;
signal TMP_T138: integer;
signal TMP_T139: integer;
signal TMP_T140: integer;
signal TMP_T141: integer;
signal TMP_T142: integer;
signal TMP_T143: integer;
signal TMP_T144: integer;
signal TMP_T145: integer;
signal TMP_T146: integer;
signal TMP_T147: integer;
signal TMP_T148: integer;
signal TMP_T149: integer;
signal TMP_T150: integer;
signal TMP_T151: integer;
signal TMP_T152: integer;
signal TMP_T153: integer;
signal TMP_T154: integer;
signal TMP_T155: integer;
signal TMP_T156: integer;
signal TMP_T157: integer;
signal TMP_T158: integer;
signal TMP_T159: integer;
signal TMP_T160: integer;

CONSTANT CRIT_FINAL_STATE: natural := 1;
CONSTANT CRIT_S0: std_logic_vector(CRIT_FINAL_STATE downto 0) := "01";
CONSTANT CRIT_S1: std_logic_vector(CRIT_FINAL_STATE downto 0) := "10";

signal R0_C0_MAN_RST: std_logic;
signal R0_C0_reqs : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C0_acks : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C0_exits : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C0_STATE: std_logic_vector(2-1 downto 0);

signal R0_C1_MAN_RST: std_logic;
signal R0_C1_reqs : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C1_acks : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C1_exits : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C1_STATE: std_logic_vector(2-1 downto 0);

signal R0_C2_MAN_RST: std_logic;
signal R0_C2_reqs : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C2_acks : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C2_exits : std_logic_vector(R0_NUM_THREADS-1 downto 0);
signal R0_C2_STATE: std_logic_vector(2-1 downto 0);

begin

R0_C0_PROC: PROCESS
variable entered: std_logic;
variable choice: natural range 0 to R0_NUM_THREADS-1;
BEGIN
wait until CLK'event and CLK = '1';
R0_C0_acks <= (others => '0');
if RST = '1' or R0_C0_MAN_RST = '1' then
R0_C0_STATE <= CRIT_S0;
else
case R0_C0_STATE is
when CRIT_S0 =>
PRIORITY(R0_C0_reqs, entered, choice, R0_C0_acks);
if entered = '1' then
R0_C0_STATE <= CRIT_S1;
end if;
when CRIT_S1 =>
if R0_C0_exits(choice) = '1' then
R0_C0_STATE <= CRIT_S0;
end if;
when OTHERS =>
R0_C0_STATE <= CRIT_S0;
end case;
end if;
END PROCESS;

R0_C1_PROC: PROCESS
variable entered: std_logic;
variable choice: natural range 0 to R0_NUM_THREADS-1;
BEGIN
wait until CLK'event and CLK = '1';
R0_C1_acks <= (others => '0');
if RST = '1' or R0_C1_MAN_RST = '1' then
R0_C1_STATE <= CRIT_S0;
else
case R0_C1_STATE is
when CRIT_S0 =>
PRIORITY(R0_C1_reqs, entered, choice, R0_C1_acks);
if entered = '1' then
R0_C1_STATE <= CRIT_S1;
end if;
when CRIT_S1 =>
if R0_C1_exits(choice) = '1' then
R0_C1_STATE <= CRIT_S0;
end if;
when OTHERS =>
R0_C1_STATE <= CRIT_S0;
end case;
end if;
END PROCESS;

R0_C2_PROC: PROCESS
variable entered: std_logic;
variable choice: natural range 0 to R0_NUM_THREADS-1;
BEGIN
wait until CLK'event and CLK = '1';
R0_C2_acks <= (others => '0');
if RST = '1' or R0_C2_MAN_RST = '1' then
R0_C2_STATE <= CRIT_S0;
else
case R0_C2_STATE is
when CRIT_S0 =>
PRIORITY(R0_C2_reqs, entered, choice, R0_C2_acks);
if entered = '1' then
R0_C2_STATE <= CRIT_S1;
end if;
when CRIT_S1 =>
if R0_C2_exits(choice) = '1' then
R0_C2_STATE <= CRIT_S0;
end if;
when OTHERS =>
R0_C2_STATE <= CRIT_S0;
end case;
end if;
END PROCESS;


delay2_PROC: PROCESS
variable delay2_has_req: std_logic;
variable delay2_choice: natural range 0 to 3-1;
BEGIN
wait until CLK'event and CLK = '1';
delay2_acks <= (others => '0');
if RST = '1' or T0_MAN_RST = '1' then
delay2_STATE <= SHARED_S0;
else
case delay2_STATE is
when SHARED_S0 =>
PRIORITY(delay2_reqs, delay2_has_req, delay2_choice, delay2_acks);
if delay2_has_req = '1' then
delay2_STATE <= SHARED_S1;
delay2(delay2_dim_1(delay2_choice)) <= delay2_inputs(delay2_choice);
end if;
when SHARED_S1 =>
delay2_STATE <= SHARED_S0;
when OTHERS =>
delay2_STATE <= SHARED_S0;
end case;
end if;
END PROCESS;

input_sum_PROC: PROCESS
variable input_sum_has_req: std_logic;
variable input_sum_choice: natural range 0 to 3-1;
BEGIN
wait until CLK'event and CLK = '1';
input_sum_acks <= (others => '0');
if RST = '1' or T0_MAN_RST = '1' then
input_sum_STATE <= SHARED_S0;
else
case input_sum_STATE is
when SHARED_S0 =>
PRIORITY(input_sum_reqs, input_sum_has_req, input_sum_choice, input_sum_acks);
if input_sum_has_req = '1' then
input_sum_STATE <= SHARED_S1;
input_sum <= input_sum_inputs(input_sum_choice);
end if;
when SHARED_S1 =>
input_sum_STATE <= SHARED_S0;
when OTHERS =>
input_sum_STATE <= SHARED_S0;
end case;
end if;
END PROCESS;

output_sum_PROC: PROCESS
variable output_sum_has_req: std_logic;
variable output_sum_choice: natural range 0 to 3-1;
BEGIN
wait until CLK'event and CLK = '1';
output_sum_acks <= (others => '0');
if RST = '1' or T0_MAN_RST = '1' then
output_sum_STATE <= SHARED_S0;
else
case output_sum_STATE is
when SHARED_S0 =>
PRIORITY(output_sum_reqs, output_sum_has_req, output_sum_choice, output_sum_acks);
if output_sum_has_req = '1' then
output_sum_STATE <= SHARED_S1;
output_sum <= output_sum_inputs(output_sum_choice);
end if;
when SHARED_S1 =>
output_sum_STATE <= SHARED_S0;
when OTHERS =>
output_sum_STATE <= SHARED_S0;
end case;
end if;
END PROCESS;

R0_end_and(0) <= AND_REDUCE(R0_end_array(0));
R0_end_and(1) <= AND_REDUCE(R0_end_array(1));
R0_end_and(2) <= AND_REDUCE(R0_end_array(2));
R0_end_and(3) <= AND_REDUCE(R0_end_array(3));

T0: PROCESS
CONSTANT THREAD_NUM: natural := 0;
BEGIN
wait until CLK'event and CLK = '1';
DONE <= '0';
R0_start <= '0';
T1_MAN_RST <= '0';
T2_MAN_RST <= '0';
R0_C0_MAN_RST <= '0';
R0_C0_reqs(THREAD_NUM) <= '0';
R0_C0_exits(THREAD_NUM) <= '0';
R0_C1_MAN_RST <= '0';
R0_C1_reqs(THREAD_NUM) <= '0';
R0_C1_exits(THREAD_NUM) <= '0';
R0_C2_MAN_RST <= '0';
R0_C2_reqs(THREAD_NUM) <= '0';
R0_C2_exits(THREAD_NUM) <= '0';
delay2_reqs(THREAD_NUM) <= '0';
input_sum_reqs(THREAD_NUM) <= '0';
output_sum_reqs(THREAD_NUM) <= '0';
R0_end_array(0)(THREAD_NUM) <= '0';
R0_end_array(1)(THREAD_NUM) <= '0';
R0_end_array(2)(THREAD_NUM) <= '0';
R0_end_array(3)(THREAD_NUM) <= '0';
if RST = '1' or T0_MAN_RST = '1' then
T0_STATE <= T0_S0;
else
case T0_STATE is



when T0_S0 =>
if START = '1' then
T0_STATE <= T0_S1;
end if;

when T0_S1 =>
coeffa <=
(4, 1, 4, 3, 5, 4, 6, 3, 5, 3, 1, 1, 6, 3, 5, 3, 5 );
T0_STATE <= T0_S2;

when T0_S2 =>
coeffb <=
(7, 4, 3, 2, 5, 6, 7, 3, 3, 2, 6, 3, 6, 3, 6, 3 );
T0_STATE <= T0_S3;

when T0_S3 =>
delay <=
(3455, 4614, 5564, 5643, 1663, 4687, 6413, 5412, 9645, 1135, 1854, 8577, 4654,
6555, 8575, 8588, 4687 );
T0_STATE <= T0_S4;

when T0_S4 =>
order <= 16;
T0_STATE <= T0_S5;

when T0_S5 =>
if input_sum_acks(THREAD_NUM) = '1' then
input_sum_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S6;
else
input_sum_reqs(THREAD_NUM) <= '1';
input_sum_inputs(THREAD_NUM) <= 0;
end if;


when T0_S6 =>
if output_sum_acks(THREAD_NUM) = '1' then
output_sum_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S7;
else
output_sum_reqs(THREAD_NUM) <= '1';
output_sum_inputs(THREAD_NUM) <= 0;
end if;


when T0_S7 =>
R0_start <= '1';

T0_STATE <= T0_S8;

when T0_S8 =>
if R0_start = '1' then
T0_STATE <= T0_S9;
end if;

when T0_S9 =>

T0_STATE <= T0_S10;

when T0_S10 =>
R0_F0_init(THREAD_NUM) <= 0;
T0_STATE <= T0_S11;

when T0_S11 =>
j_priv(THREAD_NUM) <= R0_F0_init(THREAD_NUM);
T0_STATE <= T0_S12;

when T0_S12 =>
TMP_T19 <= order - 1;
T0_STATE <= T0_S13;

when T0_S13 =>
R0_F0_end(THREAD_NUM) <= TMP_T19;
T0_STATE <= T0_S14;

when T0_S14 =>
R0_F0_incr(THREAD_NUM) <= 1;
T0_STATE <= T0_S15;

when T0_S15 =>
TMP_T20 <= THREAD_NUM * R0_F0_incr(THREAD_NUM);
T0_STATE <= T0_S16;

when T0_S16 =>
TMP_T21 <= j_priv(THREAD_NUM) + TMP_T20;
T0_STATE <= T0_S17;

when T0_S17 =>
j_priv(THREAD_NUM) <= TMP_T21;
T0_STATE <= T0_S18;

when T0_S18 =>
TMP_T12 <= R0_F0_end(THREAD_NUM);
T0_STATE <= T0_S19;

when T0_S19 =>
if (j_priv(THREAD_NUM) < TMP_T12) then
T0_STATE <= T0_S20;
else
T0_STATE <= T0_S31;
end if;


when T0_S20 =>
TMP_T22 <= delay(j_priv(THREAD_NUM)) * coeffb(j_priv(THREAD_NUM));
T0_STATE <= T0_S21;

when T0_S21 =>
TMP_T23 <= TMP_T22 / 1024;
T0_STATE <= T0_S22;

when T0_S22 =>
TMP_T0 <= TMP_T23;
T0_STATE <= T0_S23;

when T0_S23 =>
R0_C0_reqs(THREAD_NUM) <= '1';
if R0_C0_acks(THREAD_NUM) = '1' then
R0_C0_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S24;
end if;


when T0_S24 =>
TMP_T24 <= input_sum + TMP_T0;
T0_STATE <= T0_S25;

when T0_S25 =>
if input_sum_acks(THREAD_NUM) = '1' then
input_sum_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S26;
else
input_sum_reqs(THREAD_NUM) <= '1';
input_sum_inputs(THREAD_NUM) <= TMP_T24;
end if;


when T0_S26 =>
R0_C0_exits(THREAD_NUM) <= '1';
T0_STATE <= T0_S27;

when T0_S27 =>
R0_C0_exits(THREAD_NUM) <= '0';
T0_STATE <= T0_S28;

when T0_S28 =>
TMP_T25 <= 3 * R0_F0_incr(THREAD_NUM);
T0_STATE <= T0_S29;

when T0_S29 =>
TMP_T26 <= j_priv(THREAD_NUM) + TMP_T25;
T0_STATE <= T0_S30;

when T0_S30 =>
j_priv(THREAD_NUM) <= TMP_T26;
T0_STATE <= T0_S18;

when T0_S31 =>
R0_end_array(0)(THREAD_NUM) <= '1';
if R0_end_and(0) = '1' then
R0_end_array(0)(THREAD_NUM) <= '0';
T0_STATE <= T0_S32;
end if;

when T0_S32 =>

T0_STATE <= T0_S33;

when T0_S33 =>

T0_STATE <= T0_S34;

when T0_S34 =>
R0_F1_init(THREAD_NUM) <= 0;
T0_STATE <= T0_S35;

when T0_S35 =>
k_priv(THREAD_NUM) <= R0_F1_init(THREAD_NUM);
T0_STATE <= T0_S36;

when T0_S36 =>
R0_F1_end(THREAD_NUM) <= order;
T0_STATE <= T0_S37;

when T0_S37 =>
R0_F1_incr(THREAD_NUM) <= 1;
T0_STATE <= T0_S38;

when T0_S38 =>
TMP_T27 <= THREAD_NUM * R0_F1_incr(THREAD_NUM);
T0_STATE <= T0_S39;

when T0_S39 =>
TMP_T28 <= k_priv(THREAD_NUM) + TMP_T27;
T0_STATE <= T0_S40;

when T0_S40 =>
k_priv(THREAD_NUM) <= TMP_T28;
T0_STATE <= T0_S41;

when T0_S41 =>
TMP_T14 <= R0_F1_end(THREAD_NUM);
T0_STATE <= T0_S42;

when T0_S42 =>
if (k_priv(THREAD_NUM) < TMP_T14) then
T0_STATE <= T0_S43;
else
T0_STATE <= T0_S54;
end if;


when T0_S43 =>
TMP_T29 <= delay(k_priv(THREAD_NUM)) * coeffa(k_priv(THREAD_NUM));
T0_STATE <= T0_S44;

when T0_S44 =>
TMP_T30 <= TMP_T29 / 1024;
T0_STATE <= T0_S45;

when T0_S45 =>
TMP_T1 <= TMP_T30;
T0_STATE <= T0_S46;

when T0_S46 =>
R0_C1_reqs(THREAD_NUM) <= '1';
if R0_C1_acks(THREAD_NUM) = '1' then
R0_C1_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S47;
end if;


when T0_S47 =>
TMP_T31 <= output_sum + TMP_T1;
T0_STATE <= T0_S48;

when T0_S48 =>
if output_sum_acks(THREAD_NUM) = '1' then
output_sum_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S49;
else
output_sum_reqs(THREAD_NUM) <= '1';
output_sum_inputs(THREAD_NUM) <= TMP_T31;
end if;


when T0_S49 =>
R0_C1_exits(THREAD_NUM) <= '1';
T0_STATE <= T0_S50;

when T0_S50 =>
R0_C1_exits(THREAD_NUM) <= '0';
T0_STATE <= T0_S51;

when T0_S51 =>
TMP_T32 <= 3 * R0_F1_incr(THREAD_NUM);
T0_STATE <= T0_S52;

when T0_S52 =>
TMP_T33 <= k_priv(THREAD_NUM) + TMP_T32;
T0_STATE <= T0_S53;

when T0_S53 =>
k_priv(THREAD_NUM) <= TMP_T33;
T0_STATE <= T0_S41;

when T0_S54 =>
R0_end_array(1)(THREAD_NUM) <= '1';
if R0_end_and(1) = '1' then
R0_end_array(1)(THREAD_NUM) <= '0';
T0_STATE <= T0_S55;
end if;

when T0_S55 =>

T0_STATE <= T0_S56;

when T0_S56 =>

T0_STATE <= T0_S57;

when T0_S57 =>
R0_F2_init(THREAD_NUM) <= 0;
T0_STATE <= T0_S58;

when T0_S58 =>
i_priv(THREAD_NUM) <= R0_F2_init(THREAD_NUM);
T0_STATE <= T0_S59;

when T0_S59 =>
TMP_T34 <= order - 1;
T0_STATE <= T0_S60;

when T0_S60 =>
R0_F2_end(THREAD_NUM) <= TMP_T34;
T0_STATE <= T0_S61;

when T0_S61 =>
R0_F2_incr(THREAD_NUM) <= 1;
T0_STATE <= T0_S62;

when T0_S62 =>
TMP_T35 <= THREAD_NUM * R0_F2_incr(THREAD_NUM);
T0_STATE <= T0_S63;

when T0_S63 =>
TMP_T36 <= i_priv(THREAD_NUM) + TMP_T35;
T0_STATE <= T0_S64;

when T0_S64 =>
i_priv(THREAD_NUM) <= TMP_T36;
T0_STATE <= T0_S65;

when T0_S65 =>
TMP_T16 <= R0_F2_end(THREAD_NUM);
T0_STATE <= T0_S66;

when T0_S66 =>
if (i_priv(THREAD_NUM) < TMP_T16) then
T0_STATE <= T0_S67;
else
T0_STATE <= T0_S75;
end if;


when T0_S67 =>
R0_C2_reqs(THREAD_NUM) <= '1';
if R0_C2_acks(THREAD_NUM) = '1' then
R0_C2_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S68;
end if;


when T0_S68 =>
TMP_T37 <= i_priv(THREAD_NUM) + 1;
T0_STATE <= T0_S69;

when T0_S69 =>
if delay2_acks(THREAD_NUM) = '1' then
delay2_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S70;
else
delay2_reqs(THREAD_NUM) <= '1';
delay2_inputs(THREAD_NUM) <= delay(TMP_T37);
delay2_dim_1(THREAD_NUM) <= i_priv(THREAD_NUM);
end if;


when T0_S70 =>
R0_C2_exits(THREAD_NUM) <= '1';
T0_STATE <= T0_S71;

when T0_S71 =>
R0_C2_exits(THREAD_NUM) <= '0';
T0_STATE <= T0_S72;

when T0_S72 =>
TMP_T38 <= 3 * R0_F2_incr(THREAD_NUM);
T0_STATE <= T0_S73;

when T0_S73 =>
TMP_T39 <= i_priv(THREAD_NUM) + TMP_T38;
T0_STATE <= T0_S74;

when T0_S74 =>
i_priv(THREAD_NUM) <= TMP_T39;
T0_STATE <= T0_S65;

when T0_S75 =>
R0_end_array(2)(THREAD_NUM) <= '1';
if R0_end_and(2) = '1' then
R0_end_array(2)(THREAD_NUM) <= '0';
T0_STATE <= T0_S76;
end if;

when T0_S76 =>

T0_STATE <= T0_S77;

when T0_S77 =>
R0_end_array(3)(THREAD_NUM) <= '1';
if R0_end_and(3) = '1' then
R0_end_array(3)(THREAD_NUM) <= '0';
T0_STATE <= T0_S78;
end if;

when T0_S78 =>
T1_MAN_RST <= '1';
T2_MAN_RST <= '1';
R0_start <= '0';
T0_STATE <= T0_S79;

when T0_S79 =>
T1_MAN_RST <= '0';
T2_MAN_RST <= '0';
T0_STATE <= T0_S80;

when T0_S80 =>
if delay2_acks(THREAD_NUM) = '1' then
delay2_reqs(THREAD_NUM) <= '0';
T0_STATE <= T0_S81;
else
delay2_reqs(THREAD_NUM) <= '1';
delay2_inputs(THREAD_NUM) <= input_sum;
delay2_dim_1(THREAD_NUM) <= order;
end if;


when T0_S81 =>
TMP_T18 <= output_sum;
T0_STATE <= T0_S82;

when T0_S82 =>
OUTPUT <= TMP_T18;
DONE <= '1';
T1_MAN_RST <='1';
T2_MAN_RST <='1';


when OTHERS =>
T0_STATE <= T0_S0;
end case;
end if;
END PROCESS;

T1: PROCESS
CONSTANT THREAD_NUM: natural := 1;
BEGIN
wait until CLK'event and CLK = '1';
R0_C0_reqs(THREAD_NUM) <= '0';
R0_C0_exits(THREAD_NUM) <= '0';
R0_C1_reqs(THREAD_NUM) <= '0';
R0_C1_exits(THREAD_NUM) <= '0';
R0_C2_reqs(THREAD_NUM) <= '0';
R0_C2_exits(THREAD_NUM) <= '0';
delay2_reqs(THREAD_NUM) <= '0';
input_sum_reqs(THREAD_NUM) <= '0';
output_sum_reqs(THREAD_NUM) <= '0';
R0_end_array(0)(THREAD_NUM) <= '0';
R0_end_array(1)(THREAD_NUM) <= '0';
R0_end_array(2)(THREAD_NUM) <= '0';
R0_end_array(3)(THREAD_NUM) <= '0';
if RST = '1' or T1_MAN_RST = '1' then
T1_STATE <= T1_S0;
else
case T1_STATE is


when T1_S0 =>
if R0_start = '1' then
T1_STATE <= T1_S1;
end if;

when T1_S1 =>

T1_STATE <= T1_S2;

when T1_S2 =>
R0_F0_init(THREAD_NUM) <= 0;
T1_STATE <= T1_S3;

when T1_S3 =>
j_priv(THREAD_NUM) <= R0_F0_init(THREAD_NUM);
T1_STATE <= T1_S4;

when T1_S4 =>
TMP_T109 <= order - 1;
T1_STATE <= T1_S5;

when T1_S5 =>
R0_F0_end(THREAD_NUM) <= TMP_T109;
T1_STATE <= T1_S6;

when T1_S6 =>
R0_F0_incr(THREAD_NUM) <= 1;
T1_STATE <= T1_S7;

when T1_S7 =>
TMP_T110 <= THREAD_NUM * R0_F0_incr(THREAD_NUM);
T1_STATE <= T1_S8;

when T1_S8 =>
TMP_T111 <= j_priv(THREAD_NUM) + TMP_T110;
T1_STATE <= T1_S9;

when T1_S9 =>
j_priv(THREAD_NUM) <= TMP_T111;
T1_STATE <= T1_S10;

when T1_S10 =>
TMP_T112 <= R0_F0_end(THREAD_NUM);
T1_STATE <= T1_S11;

when T1_S11 =>
if (j_priv(THREAD_NUM) < TMP_T112) then
T1_STATE <= T1_S12;
else
T1_STATE <= T1_S23;
end if;


when T1_S12 =>
TMP_T113 <= delay(j_priv(THREAD_NUM)) * coeffb(j_priv(THREAD_NUM));
T1_STATE <= T1_S13;

when T1_S13 =>
TMP_T114 <= TMP_T113 / 1024;
T1_STATE <= T1_S14;

when T1_S14 =>
TMP_T115 <= TMP_T114;
T1_STATE <= T1_S15;

when T1_S15 =>
R0_C0_reqs(THREAD_NUM) <= '1';
if R0_C0_acks(THREAD_NUM) = '1' then
R0_C0_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S16;
end if;


when T1_S16 =>
TMP_T116 <= input_sum + TMP_T115;
T1_STATE <= T1_S17;

when T1_S17 =>
if input_sum_acks(THREAD_NUM) = '1' then
input_sum_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S18;
else
input_sum_reqs(THREAD_NUM) <= '1';
input_sum_inputs(THREAD_NUM) <= TMP_T116;
end if;


when T1_S18 =>
R0_C0_exits(THREAD_NUM) <= '1';
T1_STATE <= T1_S19;

when T1_S19 =>
R0_C0_exits(THREAD_NUM) <= '0';
T1_STATE <= T1_S20;

when T1_S20 =>
TMP_T117 <= 3 * R0_F0_incr(THREAD_NUM);
T1_STATE <= T1_S21;

when T1_S21 =>
TMP_T118 <= j_priv(THREAD_NUM) + TMP_T117;
T1_STATE <= T1_S22;

when T1_S22 =>
j_priv(THREAD_NUM) <= TMP_T118;
T1_STATE <= T1_S10;

when T1_S23 =>
R0_end_array(0)(THREAD_NUM) <= '1';
if R0_end_and(0) = '1' then
R0_end_array(0)(THREAD_NUM) <= '0';
T1_STATE <= T1_S24;
end if;

when T1_S24 =>

T1_STATE <= T1_S25;

when T1_S25 =>

T1_STATE <= T1_S26;

when T1_S26 =>
R0_F1_init(THREAD_NUM) <= 0;
T1_STATE <= T1_S27;

when T1_S27 =>
k_priv(THREAD_NUM) <= R0_F1_init(THREAD_NUM);
T1_STATE <= T1_S28;

when T1_S28 =>
R0_F1_end(THREAD_NUM) <= order;
T1_STATE <= T1_S29;

when T1_S29 =>
R0_F1_incr(THREAD_NUM) <= 1;
T1_STATE <= T1_S30;

when T1_S30 =>
TMP_T119 <= THREAD_NUM * R0_F1_incr(THREAD_NUM);
T1_STATE <= T1_S31;

when T1_S31 =>
TMP_T120 <= k_priv(THREAD_NUM) + TMP_T119;
T1_STATE <= T1_S32;

when T1_S32 =>
k_priv(THREAD_NUM) <= TMP_T120;
T1_STATE <= T1_S33;

when T1_S33 =>
TMP_T121 <= R0_F1_end(THREAD_NUM);
T1_STATE <= T1_S34;

when T1_S34 =>
if (k_priv(THREAD_NUM) < TMP_T121) then
T1_STATE <= T1_S35;
else
T1_STATE <= T1_S46;
end if;


when T1_S35 =>
TMP_T122 <= delay(k_priv(THREAD_NUM)) * coeffa(k_priv(THREAD_NUM));
T1_STATE <= T1_S36;

when T1_S36 =>
TMP_T123 <= TMP_T122 / 1024;
T1_STATE <= T1_S37;

when T1_S37 =>
TMP_T124 <= TMP_T123;
T1_STATE <= T1_S38;

when T1_S38 =>
R0_C1_reqs(THREAD_NUM) <= '1';
if R0_C1_acks(THREAD_NUM) = '1' then
R0_C1_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S39;
end if;


when T1_S39 =>
TMP_T125 <= output_sum + TMP_T124;
T1_STATE <= T1_S40;

when T1_S40 =>
if output_sum_acks(THREAD_NUM) = '1' then
output_sum_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S41;
else
output_sum_reqs(THREAD_NUM) <= '1';
output_sum_inputs(THREAD_NUM) <= TMP_T125;
end if;


when T1_S41 =>
R0_C1_exits(THREAD_NUM) <= '1';
T1_STATE <= T1_S42;

when T1_S42 =>
R0_C1_exits(THREAD_NUM) <= '0';
T1_STATE <= T1_S43;

when T1_S43 =>
TMP_T126 <= 3 * R0_F1_incr(THREAD_NUM);
T1_STATE <= T1_S44;

when T1_S44 =>
TMP_T127 <= k_priv(THREAD_NUM) + TMP_T126;
T1_STATE <= T1_S45;

when T1_S45 =>
k_priv(THREAD_NUM) <= TMP_T127;
T1_STATE <= T1_S33;

when T1_S46 =>
R0_end_array(1)(THREAD_NUM) <= '1';
if R0_end_and(1) = '1' then
R0_end_array(1)(THREAD_NUM) <= '0';
T1_STATE <= T1_S47;
end if;

when T1_S47 =>

T1_STATE <= T1_S48;

when T1_S48 =>

T1_STATE <= T1_S49;

when T1_S49 =>
R0_F2_init(THREAD_NUM) <= 0;
T1_STATE <= T1_S50;

when T1_S50 =>
i_priv(THREAD_NUM) <= R0_F2_init(THREAD_NUM);
T1_STATE <= T1_S51;

when T1_S51 =>
TMP_T128 <= order - 1;
T1_STATE <= T1_S52;

when T1_S52 =>
R0_F2_end(THREAD_NUM) <= TMP_T128;
T1_STATE <= T1_S53;

when T1_S53 =>
R0_F2_incr(THREAD_NUM) <= 1;
T1_STATE <= T1_S54;

when T1_S54 =>
TMP_T129 <= THREAD_NUM * R0_F2_incr(THREAD_NUM);
T1_STATE <= T1_S55;

when T1_S55 =>
TMP_T130 <= i_priv(THREAD_NUM) + TMP_T129;
T1_STATE <= T1_S56;

when T1_S56 =>
i_priv(THREAD_NUM) <= TMP_T130;
T1_STATE <= T1_S57;

when T1_S57 =>
TMP_T131 <= R0_F2_end(THREAD_NUM);
T1_STATE <= T1_S58;

when T1_S58 =>
if (i_priv(THREAD_NUM) < TMP_T131) then
T1_STATE <= T1_S59;
else
T1_STATE <= T1_S67;
end if;


when T1_S59 =>
R0_C2_reqs(THREAD_NUM) <= '1';
if R0_C2_acks(THREAD_NUM) = '1' then
R0_C2_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S60;
end if;


when T1_S60 =>
TMP_T132 <= i_priv(THREAD_NUM) + 1;
T1_STATE <= T1_S61;

when T1_S61 =>
if delay2_acks(THREAD_NUM) = '1' then
delay2_reqs(THREAD_NUM) <= '0';
T1_STATE <= T1_S62;
else
delay2_reqs(THREAD_NUM) <= '1';
delay2_inputs(THREAD_NUM) <= delay(TMP_T132);
delay2_dim_1(THREAD_NUM) <= i_priv(THREAD_NUM);
end if;


when T1_S62 =>
R0_C2_exits(THREAD_NUM) <= '1';
T1_STATE <= T1_S63;

when T1_S63 =>
R0_C2_exits(THREAD_NUM) <= '0';
T1_STATE <= T1_S64;

when T1_S64 =>
TMP_T133 <= 3 * R0_F2_incr(THREAD_NUM);
T1_STATE <= T1_S65;

when T1_S65 =>
TMP_T134 <= i_priv(THREAD_NUM) + TMP_T133;
T1_STATE <= T1_S66;

when T1_S66 =>
i_priv(THREAD_NUM) <= TMP_T134;
T1_STATE <= T1_S57;

when T1_S67 =>
R0_end_array(2)(THREAD_NUM) <= '1';
if R0_end_and(2) = '1' then
R0_end_array(2)(THREAD_NUM) <= '0';
T1_STATE <= T1_S68;
end if;

when T1_S68 =>

T1_STATE <= T1_S69;

when T1_S69 =>
R0_end_array(3)(THREAD_NUM) <= '1';
if R0_end_and(3) = '1' then
R0_end_array(3)(THREAD_NUM) <= '0';
T1_STATE <= T1_S70;
end if;

when T1_S70 =>

T1_STATE <= T1_S71;

when T1_S71 =>

T1_STATE <= T1_S72;

when T1_S72 =>


when OTHERS =>
T1_STATE <= T1_S0;
end case;
end if;
END PROCESS;

T2: PROCESS
CONSTANT THREAD_NUM: natural := 2;
BEGIN
wait until CLK'event and CLK = '1';
R0_C0_reqs(THREAD_NUM) <= '0';
R0_C0_exits(THREAD_NUM) <= '0';
R0_C1_reqs(THREAD_NUM) <= '0';
R0_C1_exits(THREAD_NUM) <= '0';
R0_C2_reqs(THREAD_NUM) <= '0';
R0_C2_exits(THREAD_NUM) <= '0';
delay2_reqs(THREAD_NUM) <= '0';
input_sum_reqs(THREAD_NUM) <= '0';
output_sum_reqs(THREAD_NUM) <= '0';
R0_end_array(0)(THREAD_NUM) <= '0';
R0_end_array(1)(THREAD_NUM) <= '0';
R0_end_array(2)(THREAD_NUM) <= '0';
R0_end_array(3)(THREAD_NUM) <= '0';
if RST = '1' or T2_MAN_RST = '1' then
T2_STATE <= T2_S0;
else
case T2_STATE is


when T2_S0 =>
if R0_start = '1' then
T2_STATE <= T2_S1;
end if;

when T2_S1 =>

T2_STATE <= T2_S2;

when T2_S2 =>
R0_F0_init(THREAD_NUM) <= 0;
T2_STATE <= T2_S3;

when T2_S3 =>
j_priv(THREAD_NUM) <= R0_F0_init(THREAD_NUM);
T2_STATE <= T2_S4;

when T2_S4 =>
TMP_T135 <= order - 1;
T2_STATE <= T2_S5;

when T2_S5 =>
R0_F0_end(THREAD_NUM) <= TMP_T135;
T2_STATE <= T2_S6;

when T2_S6 =>
R0_F0_incr(THREAD_NUM) <= 1;
T2_STATE <= T2_S7;

when T2_S7 =>
TMP_T136 <= THREAD_NUM * R0_F0_incr(THREAD_NUM);
T2_STATE <= T2_S8;

when T2_S8 =>
TMP_T137 <= j_priv(THREAD_NUM) + TMP_T136;
T2_STATE <= T2_S9;

when T2_S9 =>
j_priv(THREAD_NUM) <= TMP_T137;
T2_STATE <= T2_S10;

when T2_S10 =>
TMP_T138 <= R0_F0_end(THREAD_NUM);
T2_STATE <= T2_S11;

when T2_S11 =>
if (j_priv(THREAD_NUM) < TMP_T138) then
T2_STATE <= T2_S12;
else
T2_STATE <= T2_S23;
end if;


when T2_S12 =>
TMP_T139 <= delay(j_priv(THREAD_NUM)) * coeffb(j_priv(THREAD_NUM));
T2_STATE <= T2_S13;

when T2_S13 =>
TMP_T140 <= TMP_T139 / 1024;
T2_STATE <= T2_S14;

when T2_S14 =>
TMP_T141 <= TMP_T140;
T2_STATE <= T2_S15;

when T2_S15 =>
R0_C0_reqs(THREAD_NUM) <= '1';
if R0_C0_acks(THREAD_NUM) = '1' then
R0_C0_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S16;
end if;


when T2_S16 =>
TMP_T142 <= input_sum + TMP_T141;
T2_STATE <= T2_S17;

when T2_S17 =>
if input_sum_acks(THREAD_NUM) = '1' then
input_sum_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S18;
else
input_sum_reqs(THREAD_NUM) <= '1';
input_sum_inputs(THREAD_NUM) <= TMP_T142;
end if;


when T2_S18 =>
R0_C0_exits(THREAD_NUM) <= '1';
T2_STATE <= T2_S19;

when T2_S19 =>
R0_C0_exits(THREAD_NUM) <= '0';
T2_STATE <= T2_S20;

when T2_S20 =>
TMP_T143 <= 3 * R0_F0_incr(THREAD_NUM);
T2_STATE <= T2_S21;

when T2_S21 =>
TMP_T144 <= j_priv(THREAD_NUM) + TMP_T143;
T2_STATE <= T2_S22;

when T2_S22 =>
j_priv(THREAD_NUM) <= TMP_T144;
T2_STATE <= T2_S10;

when T2_S23 =>
R0_end_array(0)(THREAD_NUM) <= '1';
if R0_end_and(0) = '1' then
R0_end_array(0)(THREAD_NUM) <= '0';
T2_STATE <= T2_S24;
end if;

when T2_S24 =>

T2_STATE <= T2_S25;

when T2_S25 =>

T2_STATE <= T2_S26;

when T2_S26 =>
R0_F1_init(THREAD_NUM) <= 0;
T2_STATE <= T2_S27;

when T2_S27 =>
k_priv(THREAD_NUM) <= R0_F1_init(THREAD_NUM);
T2_STATE <= T2_S28;

when T2_S28 =>
R0_F1_end(THREAD_NUM) <= order;
T2_STATE <= T2_S29;

when T2_S29 =>
R0_F1_incr(THREAD_NUM) <= 1;
T2_STATE <= T2_S30;

when T2_S30 =>
TMP_T145 <= THREAD_NUM * R0_F1_incr(THREAD_NUM);
T2_STATE <= T2_S31;

when T2_S31 =>
TMP_T146 <= k_priv(THREAD_NUM) + TMP_T145;
T2_STATE <= T2_S32;

when T2_S32 =>
k_priv(THREAD_NUM) <= TMP_T146;
T2_STATE <= T2_S33;

when T2_S33 =>
TMP_T147 <= R0_F1_end(THREAD_NUM);
T2_STATE <= T2_S34;

when T2_S34 =>
if (k_priv(THREAD_NUM) < TMP_T147) then
T2_STATE <= T2_S35;
else
T2_STATE <= T2_S46;
end if;


when T2_S35 =>
TMP_T148 <= delay(k_priv(THREAD_NUM)) * coeffa(k_priv(THREAD_NUM));
T2_STATE <= T2_S36;

when T2_S36 =>
TMP_T149 <= TMP_T148 / 1024;
T2_STATE <= T2_S37;

when T2_S37 =>
TMP_T150 <= TMP_T149;
T2_STATE <= T2_S38;

when T2_S38 =>
R0_C1_reqs(THREAD_NUM) <= '1';
if R0_C1_acks(THREAD_NUM) = '1' then
R0_C1_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S39;
end if;


when T2_S39 =>
TMP_T151 <= output_sum + TMP_T150;
T2_STATE <= T2_S40;

when T2_S40 =>
if output_sum_acks(THREAD_NUM) = '1' then
output_sum_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S41;
else
output_sum_reqs(THREAD_NUM) <= '1';
output_sum_inputs(THREAD_NUM) <= TMP_T151;
end if;


when T2_S41 =>
R0_C1_exits(THREAD_NUM) <= '1';
T2_STATE <= T2_S42;

when T2_S42 =>
R0_C1_exits(THREAD_NUM) <= '0';
T2_STATE <= T2_S43;

when T2_S43 =>
TMP_T152 <= 3 * R0_F1_incr(THREAD_NUM);
T2_STATE <= T2_S44;

when T2_S44 =>
TMP_T153 <= k_priv(THREAD_NUM) + TMP_T152;
T2_STATE <= T2_S45;

when T2_S45 =>
k_priv(THREAD_NUM) <= TMP_T153;
T2_STATE <= T2_S33;

when T2_S46 =>
R0_end_array(1)(THREAD_NUM) <= '1';
if R0_end_and(1) = '1' then
R0_end_array(1)(THREAD_NUM) <= '0';
T2_STATE <= T2_S47;
end if;

when T2_S47 =>

T2_STATE <= T2_S48;

when T2_S48 =>

T2_STATE <= T2_S49;

when T2_S49 =>
R0_F2_init(THREAD_NUM) <= 0;
T2_STATE <= T2_S50;

when T2_S50 =>
i_priv(THREAD_NUM) <= R0_F2_init(THREAD_NUM);
T2_STATE <= T2_S51;

when T2_S51 =>
TMP_T154 <= order - 1;
T2_STATE <= T2_S52;

when T2_S52 =>
R0_F2_end(THREAD_NUM) <= TMP_T154;
T2_STATE <= T2_S53;

when T2_S53 =>
R0_F2_incr(THREAD_NUM) <= 1;
T2_STATE <= T2_S54;

when T2_S54 =>
TMP_T155 <= THREAD_NUM * R0_F2_incr(THREAD_NUM);
T2_STATE <= T2_S55;

when T2_S55 =>
TMP_T156 <= i_priv(THREAD_NUM) + TMP_T155;
T2_STATE <= T2_S56;

when T2_S56 =>
i_priv(THREAD_NUM) <= TMP_T156;
T2_STATE <= T2_S57;

when T2_S57 =>
TMP_T157 <= R0_F2_end(THREAD_NUM);
T2_STATE <= T2_S58;

when T2_S58 =>
if (i_priv(THREAD_NUM) < TMP_T157) then
T2_STATE <= T2_S59;
else
T2_STATE <= T2_S67;
end if;


when T2_S59 =>
R0_C2_reqs(THREAD_NUM) <= '1';
if R0_C2_acks(THREAD_NUM) = '1' then
R0_C2_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S60;
end if;


when T2_S60 =>
TMP_T158 <= i_priv(THREAD_NUM) + 1;
T2_STATE <= T2_S61;

when T2_S61 =>
if delay2_acks(THREAD_NUM) = '1' then
delay2_reqs(THREAD_NUM) <= '0';
T2_STATE <= T2_S62;
else
delay2_reqs(THREAD_NUM) <= '1';
delay2_inputs(THREAD_NUM) <= delay(TMP_T158);
delay2_dim_1(THREAD_NUM) <= i_priv(THREAD_NUM);
end if;


when T2_S62 =>
R0_C2_exits(THREAD_NUM) <= '1';
T2_STATE <= T2_S63;

when T2_S63 =>
R0_C2_exits(THREAD_NUM) <= '0';
T2_STATE <= T2_S64;

when T2_S64 =>
TMP_T159 <= 3 * R0_F2_incr(THREAD_NUM);
T2_STATE <= T2_S65;

when T2_S65 =>
TMP_T160 <= i_priv(THREAD_NUM) + TMP_T159;
T2_STATE <= T2_S66;

when T2_S66 =>
i_priv(THREAD_NUM) <= TMP_T160;
T2_STATE <= T2_S57;

when T2_S67 =>
R0_end_array(2)(THREAD_NUM) <= '1';
if R0_end_and(2) = '1' then
R0_end_array(2)(THREAD_NUM) <= '0';
T2_STATE <= T2_S68;
end if;

when T2_S68 =>

T2_STATE <= T2_S69;

when T2_S69 =>
R0_end_array(3)(THREAD_NUM) <= '1';
if R0_end_and(3) = '1' then
R0_end_array(3)(THREAD_NUM) <= '0';
T2_STATE <= T2_S70;
end if;

when T2_S70 =>

T2_STATE <= T2_S71;

when T2_S71 =>

T2_STATE <= T2_S72;

when T2_S72 =>


when OTHERS =>
T2_STATE <= T2_S0;
end case;
end if;
END PROCESS;

end rtl;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

PACKAGE type_const_pkg is

type int_array_1d is array(natural range <>) of integer;
type int_array_2d is array(natural range <>,natural range <>) of integer;
type nat_array_1d is array(natural range <>) of integer;

CONSTANT INT_WIDTH:integer := 32;


procedure ORREDUCE(ARG: IN std_logic_vector; signal RESULT: out std_logic);
procedure ANDREDUCE(ARG: IN std_logic_vector; signal RESULT: out std_logic);
procedure PRIORITY(ARG: IN std_logic_vector; variable RESULT: out std_logic; variable CHOICE: out natural; signal SEL: out std_logic_vector);

END package type_const_pkg;


package body type_const_pkg is

procedure ORREDUCE
(ARG: IN std_logic_vector;
signal RESULT: out std_logic) is
variable tmp : std_logic;
begin
tmp := '0';
for I in ARG'range loop
tmp := tmp or ARG(I);
end loop;
RESULT <= tmp;
end ORREDUCE;

procedure ANDREDUCE
(ARG: IN std_logic_vector;
signal RESULT: out std_logic) is
variable tmp : std_logic;
begin
tmp := '1';
for I in ARG'range loop
tmp := tmp and ARG(I);
end loop;
RESULT <= tmp;
end ANDREDUCE;

procedure PRIORITY
(ARG: IN std_logic_vector;
variable RESULT: out std_logic;
variable CHOICE: out natural;
signal SEL: out std_logic_vector) is
variable tmp : std_logic;
variable choice_tmp: natural range ARG'range;
variable SEL_tmp : std_logic_vector(ARG'range);
begin
tmp := '0';
SEL_tmp := (others => '0');
for I in ARG'range loop
if ARG(I) = '1' then
tmp := '1';
choice_tmp:= I;
SEL_tmp(I) := '1';
exit;
end if;
end loop;
RESULT := tmp;
CHOICE := choice_tmp;
SEL <= SEL_tmp;
end PRIORITY;

end package body type_const_pkg;
 
M

Mike Treseler

Leow said:
The problem is that a particular 32-bit integer
register is assigned a constant value of 1 for post-place-and-route
simulation and also on my RC100 board(stuck in infinite loop with no
output because of it). However, the register output correctly in
behavioral simulation.
Click to expand...

I would suspect a synchronization or Fmax problem.
Did static timing pass?
Any help to see where the problem lies is deeply appreciated!
Click to expand...

I will presume you actually
compiled your package before main
rather than the order shown in your code.

This code is an good example of the fact
that a state machine is not the
optimum description style for
a large shift register.

-- Mike Treseler
 

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