Using carry-in adders with Synopsys

Discussion in 'VHDL' started by Tuukka Toivonen, Dec 1, 2003.

  1. I'm trying to get Synopsys Design Compiler to synthesize
    an adder where I can control the carry-in input. The manual
    says:

    >>>>

    Merging Cascaded Adders With a Carry
    If your design has two cascaded adders and one has a bit input, VHDL
    Compiler replaces the two adders with a simple adder that has a carry
    input.
    Example: z <= a + b + cin;
    <<<<

    Now, "cin" can not be of type "bit", because bits can not be added,
    right? So I have tried using other types
    (natural range 0 to 1, unsigned(0 downto 0))
    but I can't get it to work: Synopsys synthesizes always two adders
    which is insane.

    Does anyone know how to make it to synthesize only one adder
    e.g. from the following code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.NUMERIC_STD.all;
    entity CADD is port(
    A: in unsigned(23 downto 0);
    B: in unsigned(23 downto 0);
    C: in std_ulogic;
    R: out unsigned(23 downto 0));
    end;
    architecture RTL of CADD is
    function caddf(A: unsigned(23 downto 0); B: unsigned(23 downto 0); C : std_ulogic) return unsigned is
    variable n : natural range 0 to 1;
    variable r : unsigned(23 downto 0);
    begin
    if C='0' then
    n := 0;
    else
    n := 1;
    end if;
    r := A + B + n;
    return r;
    end;
    begin
    R <= caddf(A,B,C);
    end;
     
    Tuukka Toivonen, Dec 1, 2003
    #1
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  2. The following may help:
    res:=(l&'1')+(r&cin);

    Notice that the operands, l and r, are extended on the right with '1' and
    'cin' rsp.
    (types of l, r and res are unsigned)
    The LSB bit of res is not be used.

    Egbert Molenkamp

    "Tuukka Toivonen" <> schreef in
    bericht news:...
    > I'm trying to get Synopsys Design Compiler to synthesize
    > an adder where I can control the carry-in input. The manual
    > says:
    >
    > >>>>

    > Merging Cascaded Adders With a Carry
    > If your design has two cascaded adders and one has a bit input, VHDL
    > Compiler replaces the two adders with a simple adder that has a carry
    > input.
    > Example: z <= a + b + cin;
    > <<<<
    >
    > Now, "cin" can not be of type "bit", because bits can not be added,
    > right? So I have tried using other types
    > (natural range 0 to 1, unsigned(0 downto 0))
    > but I can't get it to work: Synopsys synthesizes always two adders
    > which is insane.
    >
    > Does anyone know how to make it to synthesize only one adder
    > e.g. from the following code:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.NUMERIC_STD.all;
    > entity CADD is port(
    > A: in unsigned(23 downto 0);
    > B: in unsigned(23 downto 0);
    > C: in std_ulogic;
    > R: out unsigned(23 downto 0));
    > end;
    > architecture RTL of CADD is
    > function caddf(A: unsigned(23 downto 0); B: unsigned(23 downto 0); C :

    std_ulogic) return unsigned is
    > variable n : natural range 0 to 1;
    > variable r : unsigned(23 downto 0);
    > begin
    > if C='0' then
    > n := 0;
    > else
    > n := 1;
    > end if;
    > r := A + B + n;
    > return r;
    > end;
    > begin
    > R <= caddf(A,B,C);
    > end;
     
    Egbert Molenkamp, Dec 1, 2003
    #2
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  3. In article <bqg8ui$88b$>, Egbert Molenkamp wrote:
    > The following may help:
    > res:=(l&'1')+(r&cin);


    Thanks! This made my design 22% smaller. I thought about this myself
    too but it feels a bit clumsy compared to if the synthesizer could
    infer it more automatically... but this will do it for now.
     
    Tuukka Toivonen, Dec 2, 2003
    #3
  4. Tuukka Toivonen

    Ian Poole Guest

    In Synopsys Design Analyzer, set the variable "hdlin_use_cin" to "TRUE".
    When I looked at the full list of variables using the Design Analyzer GUI, I
    could only find a variable called "hdlin_use_carry_in". This second variable
    appears to have no effect!

    There is, of course, an issue with synthesis tool portability if you go
    setting variables in the Synopsys tool - the solution Egbert gave is
    portable, but slightly harder VHDL...

    Ian
    --
    Ian Poole, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.


    "Tuukka Toivonen" <> wrote in
    message news:...
    > I'm trying to get Synopsys Design Compiler to synthesize
    > an adder where I can control the carry-in input. The manual
    > says:
    >
    > >>>>

    > Merging Cascaded Adders With a Carry
    > If your design has two cascaded adders and one has a bit input, VHDL
    > Compiler replaces the two adders with a simple adder that has a carry
    > input.
    > Example: z <= a + b + cin;
    > <<<<
    >
    > Now, "cin" can not be of type "bit", because bits can not be added,
    > right? So I have tried using other types
    > (natural range 0 to 1, unsigned(0 downto 0))
    > but I can't get it to work: Synopsys synthesizes always two adders
    > which is insane.
    >
    > Does anyone know how to make it to synthesize only one adder
    > e.g. from the following code:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.NUMERIC_STD.all;
    > entity CADD is port(
    > A: in unsigned(23 downto 0);
    > B: in unsigned(23 downto 0);
    > C: in std_ulogic;
    > R: out unsigned(23 downto 0));
    > end;
    > architecture RTL of CADD is
    > function caddf(A: unsigned(23 downto 0); B: unsigned(23 downto 0); C :

    std_ulogic) return unsigned is
    > variable n : natural range 0 to 1;
    > variable r : unsigned(23 downto 0);
    > begin
    > if C='0' then
    > n := 0;
    > else
    > n := 1;
    > end if;
    > r := A + B + n;
    > return r;
    > end;
    > begin
    > R <= caddf(A,B,C);
    > end;
     
    Ian Poole, Dec 2, 2003
    #4
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