Using numeric_std packages

Discussion in 'VHDL' started by hssig, Jun 12, 2012.

  1. hssig

    hssig Guest

    Hi,

    I am trying to use the VHDL-2008 library "numeric_std_unsigned" to
    increment a std_logic_vector by one:

    use ieee.numeric_std_unsigned.all;

    signal vec : std_logic_vector(15 downto 0) := (others => '0');

    vec <= vec + 1 when rising_edge(clk);


    Now I have in the same VHDL file the following conversion:

    constant cIniVec : std_logic_vector(15 downto 0) :=
    std_logic_vector(to_unsigned(1,16));


    That means that I have to include both libraries:
    use ieee.numeric_std.all;
    use ieee.numeric_std_unsigned.all;

    Do I use the packages how nature intended it?

    Cheers, hssig
     
    hssig, Jun 12, 2012
    #1
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  2. hssig

    nivparsons Guest

    On Tuesday, June 12, 2012 12:57:25 PM UTC+1, hssig wrote:
    > Hi,
    >
    > I am trying to use the VHDL-2008 library "numeric_std_unsigned" to
    > increment a std_logic_vector by one:
    >
    > use ieee.numeric_std_unsigned.all;
    >
    > signal vec : std_logic_vector(15 downto 0) := (others => '0');
    >
    > vec <= vec + 1 when rising_edge(clk);
    >
    >
    > Now I have in the same VHDL file the following conversion:
    >
    > constant cIniVec : std_logic_vector(15 downto 0) :=
    > std_logic_vector(to_unsigned(1,16));
    >
    >
    > That means that I have to include both libraries:
    > use ieee.numeric_std.all;
    > use ieee.numeric_std_unsigned.all;
    >
    > Do I use the packages how nature intended it?
    >
    > Cheers, hssig


    You can do something like this:
    my_SLV <= SLV(UNSIGNED(my_SLV) + 1);

    where SLV is STD_LOGIC_VECTOR, my_SLV is you vector/signal and then you only need the NUMERIC_STD package. (I think)!
     
    nivparsons, Jun 12, 2012
    #2
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  3. hssig

    KJ Guest

    On Tuesday, June 12, 2012 7:57:25 AM UTC-4, hssig wrote:
    > Hi,
    >
    > I am trying to use the VHDL-2008 library "numeric_std_unsigned" to
    > increment a std_logic_vector by one:
    >
    > use ieee.numeric_std_unsigned.all;
    >
    > signal vec : std_logic_vector(15 downto 0) := (others => '0');
    >
    > vec <= vec + 1 when rising_edge(clk);
    >
    >
    > Now I have in the same VHDL file the following conversion:
    >
    > constant cIniVec : std_logic_vector(15 downto 0) :=
    > std_logic_vector(to_unsigned(1,16));
    >
    >
    > That means that I have to include both libraries:
    > use ieee.numeric_std.all;
    > use ieee.numeric_std_unsigned.all;
    >
    > Do I use the packages how nature intended it?
    >


    No you're not. You should declare vec (and cIniVec) to be of type unsigned.. std_logic_vector is used for an arbitrary collection of bits that have no numeric interpretation as well as for interfacing to the outside world. Your usage doesn't meet either criteria. Also, simply use ieee.numeric_std..all

    Kevin Jennings
     
    KJ, Jun 13, 2012
    #3
  4. hssig

    hssig Guest

    As I already mentioned:

    I am trying to increment a std_logic_vector by one (not possible with "numeric_std" but with "numeric_std_unsigned") in a testbench file.
    At the same time I want to use conversions that are part of "numric_std" but
    not of "numeric_std_unsigned", for example conversion functino "to_unsigend" of an integer.

    So how can I use both?

    Cheers, hssig
     
    hssig, Jun 18, 2012
    #4
  5. hssig

    KJ Guest

    On Monday, June 18, 2012 3:36:50 AM UTC-4, hssig wrote:
    > As I already mentioned:
    >
    > I am trying to increment a std_logic_vector by one (not possible with "numeric_std" but with "numeric_std_unsigned") in a testbench file.
    > At the same time I want to use conversions that are part of "numric_std" but
    > not of "numeric_std_unsigned", for example conversion functino "to_unsigend" of an integer.
    >
    > So how can I use both?
    >


    I already posted the best way to do that which is to change the type of the signal to unsigned rather than std_logic_vector.

    The next best way is to cast them to the proper type

    signal vec : std_logic_vector(15 downto 0) := (others => '0');
    vec <= std_logic_vector(unsigned(vec) + 1) when rising_edge(clk);

    Using ieee.numeric_std.all only

    Kevin Jennings
     
    KJ, Jun 18, 2012
    #5
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