Using Opencores I2S master

Discussion in 'VHDL' started by cbr_929rr, Oct 18, 2006.

  1. cbr_929rr

    cbr_929rr Guest

    I'm trying to use the Opencores I2S master logic as the driver for my
    test platform.

    The core came configured with SCK = 2.77 MHz and WS(left/right clock)=
    69.44 KHz.


    I would like to be able to reconfigure the core to generate SCK=3.07MHz

    and WS=48 KHz.


    I played around with the conf variable but could not get the ratio I'm
    looking for.

    Will read the documentation but an explanation would certainly help.


    Thanks
    cbr_929rr, Oct 18, 2006
    #1
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  2. cbr_929rr

    cbr_929rr Guest

    According to the manual,
    The sample rate is given by bit_rate/(RES * 2)

    If I choose the sample rate to be 48 KHz, and the resolution is
    20-bits,
    the bit rate would be 1.92 Mbps.

    However, the RATIO would then be calculated as follows.

    RATIO= (wishbone_bus_clock - (sample_rate * RES * 8)) /
    (sample_rate * RES * 4)

    wishbone_bus_clock= 50 MHz
    sample rate = 48 KHz
    RES=20 bits

    which would then be equal to ~22 (10110)
    This is not giving me the values of 48KHz for WS and 3.072 MHz for
    i2s_sck.
    I am missing something and really need some help.

    Thanks,
    cbr


    cbr_929rr wrote:
    > I'm trying to use the Opencores I2S master logic as the driver for my
    > test platform.
    >
    > The core came configured with SCK = 2.77 MHz and WS(left/right clock)=
    > 69.44 KHz.
    >
    >
    > I would like to be able to reconfigure the core to generate SCK=3.07MHz
    >
    > and WS=48 KHz.
    >
    >
    > I played around with the conf variable but could not get the ratio I'm
    > looking for.
    >
    > Will read the documentation but an explanation would certainly help.
    >
    >
    > Thanks
    cbr_929rr, Oct 19, 2006
    #2
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  3. cbr_929rr

    Andy Peters Guest

    cbr_929rr wrote:
    > I'm trying to use the Opencores I2S master logic as the driver for my
    > test platform.


    Why do you need a special I2S core? It's not much more than a couple
    of shift registers.

    -a
    Andy Peters, Oct 23, 2006
    #3
  4. cbr_929rr

    cbr_929rr Guest

    I want to be able to generate close to real I2S transactions that we
    will be having in real hardware.

    Further, I would like to use Opencores since it is already proven to
    work.

    I would be thankful if I can get some help on how to re-configure the
    core by referring to the configurable parameters in the example I've
    mentioned previously.


    I'm sure that there are atleast a few people in this group who have
    used this core and know how it works.
    It's just that I have not had any luck yet in finding the answer even
    though I posted this question on comp.arch.fpga, vhdl, embedded and
    even on opencores
    forum/usenet groups.

    Cbr.

    Andy Peters wrote:
    > cbr_929rr wrote:
    > > I'm trying to use the Opencores I2S master logic as the driver for my
    > > test platform.

    >
    > Why do you need a special I2S core? It's not much more than a couple
    > of shift registers.
    >
    > -a
    cbr_929rr, Oct 24, 2006
    #4
  5. cbr_929rr

    cbr_929rr Guest

    I changed the conf ratio to "00001011", bypassed the WB_interface and
    it started working.
    The ACLK and LRCLK seemed to be what I expected. However, the SCLK was
    not.
    I used a FIFO to latch the data and read it out based on ACLK.

    Thanks.

    Cbr

    cbr_929rr wrote:
    > I want to be able to generate close to real I2S transactions that we
    > will be having in real hardware.
    >
    > Further, I would like to use Opencores since it is already proven to
    > work.
    >
    > I would be thankful if I can get some help on how to re-configure the
    > core by referring to the configurable parameters in the example I've
    > mentioned previously.
    >
    >
    > I'm sure that there are atleast a few people in this group who have
    > used this core and know how it works.
    > It's just that I have not had any luck yet in finding the answer even
    > though I posted this question on comp.arch.fpga, vhdl, embedded and
    > even on opencores
    > forum/usenet groups.
    >
    > Cbr.
    >
    > Andy Peters wrote:
    > > cbr_929rr wrote:
    > > > I'm trying to use the Opencores I2S master logic as the driver for my
    > > > test platform.

    > >
    > > Why do you need a special I2S core? It's not much more than a couple
    > > of shift registers.
    > >
    > > -a
    cbr_929rr, Oct 27, 2006
    #5
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