Variable Subtype Problem

Discussion in 'VHDL' started by Takuon Soho, Mar 1, 2005.

  1. Takuon Soho

    Takuon Soho Guest

    I have a 12 bit counter whoose value
    needs to be output to 12 output pins
    of a cpld
    when flag signal goes high (see Process code below).

    But I can't figure out how to output my_counter
    to a std_logic_vector
    because it is a subtype of integer.

    I tried things like
    bus_0_11 <= std_logic_vector(counter_ty my_counter);
    without compilation success.

    Anyone know how to do this?

    Thanks
    Tak

    code follows:

    entity count12 is port (
    clk : in std_logic;
    ....
    bus_0_11: out std_logic_vector(11 downto 0)
    );
    end count12;


    Process(clk,flag)

    -- my counter variable declaration
    subtype counter_ty is integer range 0 to 4095; -- 12 bit counter,
    integer
    variable my_counter : counter_ty := 0;

    begin

    .....

    if (flag = '1') then -- flag hi, output count to bus
    bus_0_11 <= std_logic_vector(counter_ty my_counter);
    flag = '0';
    elsif (clk'event and clk = '1') then
    my_counter = my_counter + 1;
    end if;

    end process;
    Takuon Soho, Mar 1, 2005
    #1
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  2. Takuon Soho

    aaaaaa Guest

    I am unable to understand that why u are defing the counter value as
    integer . U can define as std_logic_vector .
    or
    U can use the conversion function as--
    CONV_STD_LOGIC_VECTOR conversion function:

    ENTITY adder IS
    PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
    result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
    END adder;

    ARCHITECTURE maxpld OF adder IS
    BEGIN
    result <= CONV_STD_LOGIC_VECTOR(op1 + op2, 8);
    END maxpld;

    I have updated your code pl check -
    LIBRARY IEEE ;
    USE IEEE.STD_LOGIC_1164.ALL ;
    USE IEEE.STD_LOGIC_ARITH.ALL ;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
    entity count12 is
    port (
    clk : in std_logic;
    bus_0_11: out std_logic_vector(11 downto 0)

    );
    end count12;
    architecture beh of count12 is
    signal flag : std_logic;
    begin
    Process(clk,flag)

    -- my counter variable declaration
    subtype counter_ty is integer range 0 to 4095; -- 12 bit counter,

    variable my_counter : counter_ty := 0;

    begin



    if (flag = '1') then -- flag hi, output count to bus
    bus_0_11 <= conv_std_logic_vector(my_counter, 12);
    flag <= '0';
    elsif (clk'event and clk = '1') then
    my_counter := my_counter + 1;
    end if;

    end process;

    end beh;
    aaaaaa, Mar 1, 2005
    #2
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  3. Hi ,

    Dont use ieee.std_logic_arith.all or ieee.std_lgoci_arith.all for
    arithematic operation on std_logic types ......

    Package std_logic_arith is developed by SYNOPSYS before the IEEE
    packages were available. It should not be used since now that there is
    an official IEEE standard. Instead use ieee.numeric_std.all or
    ieee.numeric_bit.all for such types arithematic types...

    Check this for many other such packages

    http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

    About the code for counter .... he is using flag as a asynchronous
    signal to read the data to output port but if at the same time clk
    goes high then counter is not incremeted ... I dont think this is what
    intended there..

    Regards,
    Mohammed Khader.
    Mohammed A khader, Mar 1, 2005
    #3
  4. Well if you're outputting it to 12 output pins it looks like you're
    using GRAY code or something like it. i.e.
    1 => 000000000001
    2 => 000000000010
    2 => 000000000100
    ---or---
    1 => 000000000001
    2 => 000000000011
    2 => 000000000111

    If this is the case, just use a lookup table
    ie case intIn is
    when 0=> vecOut <= "000000000000";
    when 1=> vecOut <= "000000000001";
    etc...

    This is a bit of a waste of resources though when 4 pins would do just
    as well using the simpler conv_std_integer function and the
    std_logic_unsigned library
    dutchgoldtony, Mar 1, 2005
    #4
  5. Takuon Soho

    Takuon Soho Guest

    Many thanks to you and everyone for advice.

    I defined counter as an integer because I wanted only 12 bits (count is
    never bigger than 4095) and I saw that a subtype
    would allow me to restrict the size to just what I needed.

    Also, I was not sure about using
    std_logic_vector as a counter because I wasn't sure if vector = vector + 1
    would result in an addition or a bit AND operation. (Easy enough for
    me to find out with a simple experiment).

    The VHDL language is so strongly typed that everything I tried with subtypes
    resulted
    in an error in the MODELSIM compiler with no real clue as to the right way.

    I will check out your suggestions, which seem to be excellent, on compiler.

    Again, thanks
    Tak


    "aaaaaa" <> wrote in message
    news:...
    >I am unable to understand that why u are defing the counter value as
    > integer . U can define as std_logic_vector .
    > or
    > U can use the conversion function as--
    > CONV_STD_LOGIC_VECTOR conversion function:
    >
    > ENTITY adder IS
    > PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
    > result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    > );
    > END adder;
    >
    > ARCHITECTURE maxpld OF adder IS
    > BEGIN
    > result <= CONV_STD_LOGIC_VECTOR(op1 + op2, 8);
    > END maxpld;
    >
    > I have updated your code pl check -
    > LIBRARY IEEE ;
    > USE IEEE.STD_LOGIC_1164.ALL ;
    > USE IEEE.STD_LOGIC_ARITH.ALL ;
    > USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
    > entity count12 is
    > port (
    > clk : in std_logic;
    > bus_0_11: out std_logic_vector(11 downto 0)
    >
    > );
    > end count12;
    > architecture beh of count12 is
    > signal flag : std_logic;
    > begin
    > Process(clk,flag)
    >
    > -- my counter variable declaration
    > subtype counter_ty is integer range 0 to 4095; -- 12 bit counter,
    >
    > variable my_counter : counter_ty := 0;
    >
    > begin
    >
    >
    >
    > if (flag = '1') then -- flag hi, output count to bus
    > bus_0_11 <= conv_std_logic_vector(my_counter, 12);
    > flag <= '0';
    > elsif (clk'event and clk = '1') then
    > my_counter := my_counter + 1;
    > end if;
    >
    > end process;
    >
    > end beh;
    >
    >
    Takuon Soho, Mar 1, 2005
    #5
  6. Takuon Soho

    Jim Lewis Guest

    Takuon,
    For more more tips see the paper,
    "VHDL Math Tricks of the Trade"

    which is available at:
    http://www.synthworks.com/papers/

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    > Many thanks to you and everyone for advice.
    >
    > I defined counter as an integer because I wanted only 12 bits (count is
    > never bigger than 4095) and I saw that a subtype
    > would allow me to restrict the size to just what I needed.
    >
    > Also, I was not sure about using
    > std_logic_vector as a counter because I wasn't sure if vector = vector + 1
    > would result in an addition or a bit AND operation. (Easy enough for
    > me to find out with a simple experiment).
    >
    > The VHDL language is so strongly typed that everything I tried with subtypes
    > resulted
    > in an error in the MODELSIM compiler with no real clue as to the right way.
    >
    > I will check out your suggestions, which seem to be excellent, on compiler.
    >
    > Again, thanks
    > Tak
    >
    >
    > "aaaaaa" <> wrote in message
    > news:...
    >
    >>I am unable to understand that why u are defing the counter value as
    >>integer . U can define as std_logic_vector .
    >>or
    >>U can use the conversion function as--
    >>CONV_STD_LOGIC_VECTOR conversion function:
    >>
    >>ENTITY adder IS
    >> PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
    >> result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    >> );
    >>END adder;
    >>
    >>ARCHITECTURE maxpld OF adder IS
    >>BEGIN
    >> result <= CONV_STD_LOGIC_VECTOR(op1 + op2, 8);
    >>END maxpld;
    >>
    >>I have updated your code pl check -
    >>LIBRARY IEEE ;
    >>USE IEEE.STD_LOGIC_1164.ALL ;
    >>USE IEEE.STD_LOGIC_ARITH.ALL ;
    >>USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
    >>entity count12 is
    >> port (
    >> clk : in std_logic;
    >> bus_0_11: out std_logic_vector(11 downto 0)
    >>
    >> );
    >>end count12;
    >>architecture beh of count12 is
    >>signal flag : std_logic;
    >>begin
    >>Process(clk,flag)
    >>
    >>-- my counter variable declaration
    >> subtype counter_ty is integer range 0 to 4095; -- 12 bit counter,
    >>
    >> variable my_counter : counter_ty := 0;
    >>
    >>begin
    >>
    >>
    >>
    >>if (flag = '1') then -- flag hi, output count to bus
    >> bus_0_11 <= conv_std_logic_vector(my_counter, 12);
    >> flag <= '0';
    >>elsif (clk'event and clk = '1') then
    >> my_counter := my_counter + 1;
    >>end if;
    >>
    >>end process;
    >>
    >>end beh;
    >>
    Jim Lewis, Mar 1, 2005
    #6
  7. Takuon Soho

    Takuon Soho Guest

    Many interesting papers there.

    Am reading.

    Thanks
    Tak

    "Jim Lewis" <> wrote in message
    news:...
    > Takuon,
    > For more more tips see the paper,
    > "VHDL Math Tricks of the Trade"
    >
    > which is available at:
    > http://www.synthworks.com/papers/
    >
    > Cheers,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    >
    >> Many thanks to you and everyone for advice.
    >>
    >> I defined counter as an integer because I wanted only 12 bits (count is
    >> never bigger than 4095) and I saw that a subtype
    >> would allow me to restrict the size to just what I needed.
    >>
    >> Also, I was not sure about using
    >> std_logic_vector as a counter because I wasn't sure if vector = vector +
    >> 1
    >> would result in an addition or a bit AND operation. (Easy enough for
    >> me to find out with a simple experiment).
    >>
    >> The VHDL language is so strongly typed that everything I tried with
    >> subtypes resulted
    >> in an error in the MODELSIM compiler with no real clue as to the right
    >> way.
    >>
    >> I will check out your suggestions, which seem to be excellent, on
    >> compiler.
    >>
    >> Again, thanks
    >> Tak
    >>
    >>
    >> "aaaaaa" <> wrote in message
    >> news:...
    >>
    >>>I am unable to understand that why u are defing the counter value as
    >>>integer . U can define as std_logic_vector .
    >>>or
    >>>U can use the conversion function as--
    >>>CONV_STD_LOGIC_VECTOR conversion function:
    >>>
    >>>ENTITY adder IS
    >>> PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
    >>> result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    >>> );
    >>>END adder;
    >>>
    >>>ARCHITECTURE maxpld OF adder IS
    >>>BEGIN
    >>> result <= CONV_STD_LOGIC_VECTOR(op1 + op2, 8);
    >>>END maxpld;
    >>>
    >>>I have updated your code pl check -
    >>>LIBRARY IEEE ;
    >>>USE IEEE.STD_LOGIC_1164.ALL ;
    >>>USE IEEE.STD_LOGIC_ARITH.ALL ;
    >>>USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
    >>>entity count12 is
    >>> port (
    >>> clk : in std_logic;
    >>> bus_0_11: out std_logic_vector(11 downto 0)
    >>>
    >>> );
    >>>end count12;
    >>>architecture beh of count12 is
    >>>signal flag : std_logic;
    >>>begin
    >>>Process(clk,flag)
    >>>
    >>>-- my counter variable declaration
    >>> subtype counter_ty is integer range 0 to 4095; -- 12 bit counter,
    >>>
    >>> variable my_counter : counter_ty := 0;
    >>>
    >>>begin
    >>>
    >>>
    >>>
    >>>if (flag = '1') then -- flag hi, output count to bus
    >>> bus_0_11 <= conv_std_logic_vector(my_counter, 12);
    >>> flag <= '0';
    >>>elsif (clk'event and clk = '1') then
    >>> my_counter := my_counter + 1;
    >>>end if;
    >>>
    >>>end process;
    >>>
    >>>end beh;
    >>>
    Takuon Soho, Mar 2, 2005
    #7
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