variable timing signal

Discussion in 'VHDL' started by Amit, Nov 1, 2007.

  1. Amit

    Amit Guest

    Hello group,

    I will appreciate it if sombody give me only hint on this question. I
    just don't get it!

    Write a complete vhdl program to generate a variable timing signal
    that has a period of 10ms if the control signal
    C is '0' and has a period of 20ms if the control signal is '1'. Both
    signals have a duty cycle of 20%. Assume that a one KHz clock signal
    Clock 1ms is avaiable.

    Your help is appreciated.

    Amit
     
    Amit, Nov 1, 2007
    #1
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  2. Amit

    KJ Guest

    "Amit" <> wrote in message
    news:...
    >
    > Hello group,
    >
    > I will appreciate it if sombody give me only hint on this question. I
    > just don't get it!
    >
    > Write a complete vhdl program to generate a variable timing signal
    > that has a period of 10ms if the control signal
    > C is '0' and has a period of 20ms if the control signal is '1'. Both
    > signals have a duty cycle of 20%. Assume that a one KHz clock signal
    > Clock 1ms is avaiable.
    >
    > Your help is appreciated.
    >
    > Amit
    >


    The problem statement you provided doesn't require the vhdl program to be
    synthesizable so below is a sketch of how one could accomplish most of what
    you asked for (left out is the 20% duty cycle). If this does need to be
    synthesizable, I'd suggest a simple counter and use the 1 ms clock period
    input (i.e. the 1KHz that I didn't need).

    signal Clock_Period: time := 10 ms;
    signal Clock: std_ulogic := '0';
    ....

    Clock_Period <= 20 ms when (C = '1') else 10 ms;
    Clock <= not(Clock) after Clock_Period;

    KJ
     
    KJ, Nov 1, 2007
    #2
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  3. Amit

    Amit Guest

    On Nov 1, 4:01 am, "KJ" <> wrote:
    > "Amit" <> wrote in message
    >
    > news:...
    >
    >
    >
    >
    >
    >
    >
    > > Hello group,

    >
    > > I will appreciate it if sombody give me only hint on this question. I
    > > just don't get it!

    >
    > > Write a complete vhdl program to generate a variable timing signal
    > > that has a period of 10ms if the control signal
    > > C is '0' and has a period of 20ms if the control signal is '1'. Both
    > > signals have a duty cycle of 20%. Assume that a one KHz clock signal
    > > Clock 1ms is avaiable.

    >
    > > Your help is appreciated.

    >
    > > Amit

    >
    > The problem statement you provided doesn't require the vhdl program to be
    > synthesizable so below is a sketch of how one could accomplish most of what
    > you asked for (left out is the 20% duty cycle). If this does need to be
    > synthesizable, I'd suggest a simple counter and use the 1 ms clock period
    > input (i.e. the 1KHz that I didn't need).
    >
    > signal Clock_Period: time := 10 ms;
    > signal Clock: std_ulogic := '0';
    > ...
    >
    > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > Clock <= not(Clock) after Clock_Period;
    >
    > KJ- Hide quoted text -
    >
    > - Show quoted text -



    Hi KJ,

    Thank you for your response. I have two questions:

    1) why did you declare clock as std_ulogic not std_logic?

    2)
    Please correct me if I'm wrong:

    I'm new to VHDL but I think since there is a sequence going on here so
    I will need to put this in a process block. Right?

    something like:

    entity ent is

    port(

    clk : in std_logic;
    q : out std_logic;
    );

    end ent;

    architecture beh of ent is
    begin

    process(clk)
    signal Clock_Period : time := 10 ms;
    signal Clock : std_ulogic := '0';
    begin

    -- Your code

    Clock_Period <= 20 ms when (C = '1') else 10 ms;
    Clock <= not(Clock) after Clock_Period;

    end process;

    q <= clock;

    end beh;


    Any advice?

    Thanks again.
     
    Amit, Nov 1, 2007
    #3
  4. Amit

    KJ Guest

    On Nov 1, 1:19 pm, Amit <> wrote:
    > On Nov 1, 4:01 am, "KJ" <> wrote:
    >
    >
    >
    >
    >
    > > "Amit" <> wrote in message

    >
    > >news:...

    >
    > > > Hello group,

    >
    > > > I will appreciate it if sombody give me only hint on this question. I
    > > > just don't get it!

    >
    > > > Write a complete vhdl program to generate a variable timing signal
    > > > that has a period of 10ms if the control signal
    > > > C is '0' and has a period of 20ms if the control signal is '1'. Both
    > > > signals have a duty cycle of 20%. Assume that a one KHz clock signal
    > > > Clock 1ms is avaiable.

    >
    > > > Your help is appreciated.

    >
    > > > Amit

    >
    > > The problem statement you provided doesn't require the vhdl program to be
    > > synthesizable so below is a sketch of how one could accomplish most of what
    > > you asked for (left out is the 20% duty cycle). If this does need to be
    > > synthesizable, I'd suggest a simple counter and use the 1 ms clock period
    > > input (i.e. the 1KHz that I didn't need).

    >
    > > signal Clock_Period: time := 10 ms;
    > > signal Clock: std_ulogic := '0';
    > > ...

    >
    > > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > > Clock <= not(Clock) after Clock_Period;

    >
    > > KJ- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Hi KJ,
    >
    > Thank you for your response. I have two questions:
    >
    > 1) why did you declare clock as std_ulogic not std_logic?

    Habit. I prefer std_ulogic over std_logic because then the compiler
    immediately flags when I have two drivers on the same net. I don't
    have to simulate and debug to find it.
    >
    > 2)
    > Please correct me if I'm wrong:
    >
    > I'm new to VHDL but I think since there is a sequence going on here so
    > I will need to put this in a process block. Right?

    No. The two signal assignments are simply concurrent signal
    assignments there is no explicit process. The full blown thing is
    shown below. Also, in the original post I had
    Clock <= not(Clock) after Clock_Period;
    which should have been
    Clock <= not(Clock) after Clock_Period / 2;


    library ieee;
    use ieee.std_logic_1164.all;
    entity ent is port(
    C: in std_ulogic;
    Q: out std_ulogic);
    end ent;
    architecture beh of ent is
    signal Clock_Period : time := 10 ms;
    signal Clock : std_ulogic := '0';
    begin
    Clock_Period <= 20 ms when (C = '1') else 10 ms;
    Clock <= not(Clock) after Clock_Period / 2;
    Q <= Clock;
    end beh;


    KJ
     
    KJ, Nov 1, 2007
    #4
  5. Amit

    beckjer Guest

    On Nov 1, 10:56 am, KJ <> wrote:
    > On Nov 1, 1:19 pm, Amit <> wrote:
    >
    >
    >
    > > On Nov 1, 4:01 am, "KJ" <> wrote:

    >
    > > > "Amit" <> wrote in message

    >
    > > >news:...

    >
    > > > > Hello group,

    >
    > > > > I will appreciate it if sombody give me only hint on this question. I
    > > > > just don't get it!

    >
    > > > > Write a complete vhdl program to generate a variable timing signal
    > > > > that has a period of 10ms if the control signal
    > > > > C is '0' and has a period of 20ms if the control signal is '1'. Both
    > > > > signals have a duty cycle of 20%. Assume that a one KHz clock signal
    > > > > Clock 1ms is avaiable.

    >
    > > > > Your help is appreciated.

    >
    > > > > Amit

    >
    > > > The problem statement you provided doesn't require the vhdl program to be
    > > > synthesizable so below is a sketch of how one could accomplish most of what
    > > > you asked for (left out is the 20% duty cycle). If this does need to be
    > > > synthesizable, I'd suggest a simple counter and use the 1 ms clock period
    > > > input (i.e. the 1KHz that I didn't need).

    >
    > > > signal Clock_Period: time := 10 ms;
    > > > signal Clock: std_ulogic := '0';
    > > > ...

    >
    > > > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > > > Clock <= not(Clock) after Clock_Period;

    >
    > > > KJ- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > Hi KJ,

    >
    > > Thank you for your response. I have two questions:

    >
    > > 1) why did you declare clock as std_ulogic not std_logic?

    >
    > Habit. I prefer std_ulogic over std_logic because then the compiler
    > immediately flags when I have two drivers on the same net. I don't
    > have to simulate and debug to find it.
    >
    > > 2)
    > > Please correct me if I'm wrong:

    >
    > > I'm new to VHDL but I think since there is a sequence going on here so
    > > I will need to put this in a process block. Right?

    >
    > No. The two signal assignments are simply concurrent signal
    > assignments there is no explicit process. The full blown thing is
    > shown below. Also, in the original post I had
    > Clock <= not(Clock) after Clock_Period;
    > which should have been
    > Clock <= not(Clock) after Clock_Period / 2;
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > entity ent is port(
    > C: in std_ulogic;
    > Q: out std_ulogic);
    > end ent;
    > architecture beh of ent is
    > signal Clock_Period : time := 10 ms;
    > signal Clock : std_ulogic := '0';
    > begin
    > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > Clock <= not(Clock) after Clock_Period / 2;
    > Q <= Clock;
    > end beh;
    >
    > KJ- Hide quoted text -
    >
    > - Show quoted text -


    That's almost correct. You forgot that Amit was looking for a duty
    cycle of 20%. The /2 makes it a 50% duty cycle.

    Another fun way would be to create 2 clock sources, 1 run at 1mS the
    other at 2mS. Feed both these clocks into a 10 decimal counter that
    flips the bit on count 2 and 10. Then use the input 'C' to select
    between the 2 clock sources.

    -jerry
     
    beckjer, Nov 2, 2007
    #5
  6. Amit

    KJ Guest

    On Nov 2, 12:33 pm, beckjer <> wrote:
    > On Nov 1, 10:56 am, KJ <> wrote:
    >
    >
    >
    >
    >
    > > On Nov 1, 1:19 pm, Amit <> wrote:

    >
    > > > On Nov 1, 4:01 am, "KJ" <> wrote:

    >
    > > > > "Amit" <> wrote in message

    >
    > > > >news:...

    >
    > > > > > Hello group,

    >
    > > > > > I will appreciate it if sombody give me only hint on this question. I
    > > > > > just don't get it!

    >
    > > > > > Write a complete vhdl program to generate a variable timing signal
    > > > > > that has a period of 10ms if the control signal
    > > > > > C is '0' and has a period of 20ms if the control signal is '1'. Both
    > > > > > signals have a duty cycle of 20%. Assume that a one KHz clock signal
    > > > > > Clock 1ms is avaiable.

    >
    > > > > > Your help is appreciated.

    >
    > > > > > Amit

    >
    > > > > The problem statement you provided doesn't require the vhdl program to be
    > > > > synthesizable so below is a sketch of how one could accomplish most of what
    > > > > you asked for (left out is the 20% duty cycle). If this does need to be
    > > > > synthesizable, I'd suggest a simple counter and use the 1 ms clock period
    > > > > input (i.e. the 1KHz that I didn't need).

    >
    > > > > signal Clock_Period: time := 10 ms;
    > > > > signal Clock: std_ulogic := '0';
    > > > > ...

    >
    > > > > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > > > > Clock <= not(Clock) after Clock_Period;

    >
    > > > > KJ- Hide quoted text -

    >
    > > > > - Show quoted text -

    >
    > > > Hi KJ,

    >
    > > > Thank you for your response. I have two questions:

    >
    > > > 1) why did you declare clock as std_ulogic not std_logic?

    >
    > > Habit. I prefer std_ulogic over std_logic because then the compiler
    > > immediately flags when I have two drivers on the same net. I don't
    > > have to simulate and debug to find it.

    >
    > > > 2)
    > > > Please correct me if I'm wrong:

    >
    > > > I'm new to VHDL but I think since there is a sequence going on here so
    > > > I will need to put this in a process block. Right?

    >
    > > No. The two signal assignments are simply concurrent signal
    > > assignments there is no explicit process. The full blown thing is
    > > shown below. Also, in the original post I had
    > > Clock <= not(Clock) after Clock_Period;
    > > which should have been
    > > Clock <= not(Clock) after Clock_Period / 2;

    >
    > > library ieee;
    > > use ieee.std_logic_1164.all;
    > > entity ent is port(
    > > C: in std_ulogic;
    > > Q: out std_ulogic);
    > > end ent;
    > > architecture beh of ent is
    > > signal Clock_Period : time := 10 ms;
    > > signal Clock : std_ulogic := '0';
    > > begin
    > > Clock_Period <= 20 ms when (C = '1') else 10 ms;
    > > Clock <= not(Clock) after Clock_Period / 2;
    > > Q <= Clock;
    > > end beh;

    >
    > > KJ- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > That's almost correct. You forgot that Amit was looking for a duty
    > cycle of 20%. The /2 makes it a 50% duty cycle.
    >

    As I mentioned in my first post, I intentionally left out the duty
    cycle requirement...you have to leave at least some of the homework
    for the student to accomplish.

    KJ
     
    KJ, Nov 2, 2007
    #6
  7. KJ wrote:
    > I prefer std_ulogic over std_logic because then the compiler
    > immediately flags when I have two drivers on the same net. I don't
    > have to simulate and debug to find it.


    Indeed, with the rare exception
    of a real tri-state port pin, there is no
    good reason *not* to use std_ulogic bits in my code.

    No are conversions needed.

    std_ulogic is 100% compatible with the
    std_logic type I often find in code by others,
    to which I must port map.

    -- Mike Treseler
     
    Mike Treseler, Nov 3, 2007
    #7
  8. Amit

    Amit Guest

    On Nov 3, 9:28 am, Mike Treseler <> wrote:
    > KJ wrote:
    > > I prefer std_ulogic over std_logic because then the compiler
    > > immediately flags when I have two drivers on the same net. I don't
    > > have to simulate and debug to find it.

    >
    > Indeed, with the rare exception
    > of a real tri-state port pin, there is no
    > good reason *not* to use std_ulogic bits in my code.
    >
    > No are conversions needed.
    >
    > std_ulogic is 100% compatible with the
    > std_logic type I often find in code by others,
    > to which I must port map.
    >
    > -- Mike Treseler



    So as conclusion using a signal of type std_ulogic is better. Right?
     
    Amit, Nov 4, 2007
    #8
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