Variable 'variable lengths'

Discussion in 'VHDL' started by Taras_96, May 8, 2005.

  1. Taras_96

    Taras_96 Guest

    Hi

    I'm writing some code for simulation only (not synthesis). Is there
    someway of declaring a unsigned variable's length in the body of a
    function? So far I haven't had any success because you need to declare
    the variable and its length before the body of the function, and you
    can't declare an unconstrained variable.

    Thanks

    Taras
     
    Taras_96, May 8, 2005
    #1
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  2. Taras_96 wrote:

    > Is there
    > someway of declaring a unsigned variable's length in the body of a
    > function?


    reference the length of the actual
    argument right in the variable declaration
    -- ...
    )
    return unsigned is
    variable reg_v : unsigned(vec_arg'range);
    begin
    -- ...

    > So far I haven't had any success because you need to declare
    > the variable and its length before the body of the function, and you
    > can't declare an unconstrained variable.


    No, but you can use an unconstrained parameter.

    -- Mike Treseler
     
    Mike Treseler, May 8, 2005
    #2
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  3. Taras_96

    Taras_96 Guest

    Thanks Mike
     
    Taras_96, May 9, 2005
    #3
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