Verilog INOUT problem!

Discussion in 'VHDL' started by thomas_ns, Dec 28, 2007.

  1. thomas_ns

    thomas_ns Guest

    Hello, everybody!

    I have to transcode some project from VHDL to Verilog.
    The problem is that I have some INOUT ports in VHDL code which I can't
    just copy to Verilog code.
    How can I do it?

    example code piece:

    ENTITY car IS

    PORT (
    RESET : IN std_logic;
    CLK : IN std_logic;
    AutoInit : IN std_logic;
    WriteDataIn : IN std_logic_vector( 7 DOWNTO 0);
    BarData : IN std_logic_vector(15 DOWNTO 0);
    UpdateAddr : IN std_logic_vector(15 DOWNTO 0);
    LoadAddr : IN std_logic_vector( 1 DOWNTO 0);
    EndOfDma : IN std_logic;
    Update : IN std_logic;

    CurrentAddr : INOUT std_logic_vector(15 DOWNTO 0)
    );

    END car;


    --**********************************************************************************************
    -- Architecture Body
    --**********************************************************************************************

    ARCHITECTURE rtl OF car IS
    BEGIN

    writeadd: PROCESS ( LoadAddr, WriteDataIn, AutoInit, BarData, EndOfDma,
    Update, CurrentAddr, UpdateAddr, CLK, RESET )

    VARIABLE next_CurrentAddr : std_logic_vector(15 DOWNTO 0);

    BEGIN

    IF (AutoInit = '1') AND (EndOfDma = '1') THEN

    next_CurrentAddr(7 DOWNTO 0) := BarData(7 DOWNTO 0);

    ELSIF (Update = '1') THEN

    next_CurrentAddr(7 DOWNTO 0) := UpdateAddr(7 DOWNTO 0);

    ELSIF (LoadAddr(0) = '1') THEN

    next_CurrentAddr(7 DOWNTO 0) := WriteDataIn(7 DOWNTO 0);

    ELSE

    next_CurrentAddr(7 DOWNTO 0) := CurrentAddr(7 DOWNTO 0);

    END IF;


    IF (AutoInit = '1') AND (EndOfDma = '1') THEN

    next_CurrentAddr(15 DOWNTO 8) := BarData(15 DOWNTO 8);

    ELSIF (Update = '1') THEN

    next_CurrentAddr(15 DOWNTO 8) := UpdateAddr(15 DOWNTO 8);

    ELSIF (LoadAddr(1) = '1') THEN

    next_CurrentAddr(15 DOWNTO 8) := WriteDataIn(7 DOWNTO 0);

    ELSE

    next_CurrentAddr(15 DOWNTO 8) := CurrentAddr(15 DOWNTO 8);

    END IF;

    IF ( RESET = '1' ) THEN -- Asynchronous clear

    CurrentAddr(15 DOWNTO 0) <= "0000000000000000";

    ELSIF (CLK'EVENT AND (CLK = '0')) THEN

    CurrentAddr(15 DOWNTO 0) <= next_CurrentAddr(15 DOWNTO 0);

    END IF;

    END PROCESS;

    END rtl;




    Kind regards
    thomas_ns

    --
    Message posted using http://www.talkaboutprogramming.com/group/comp.lang.vhdl/
    More information at http://www.talkaboutprogramming.com/faq.html
     
    thomas_ns, Dec 28, 2007
    #1
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  2. thomas_ns

    sudhi Guest

    On Dec 28, 10:01 am, "thomas_ns" <> wrote:
    > Hello, everybody!
    >
    > I have to transcode some project from VHDL to Verilog.
    > The problem is that I have some INOUT ports in VHDL code which I can't
    > just copy to Verilog code.
    > How can I do it?
    >
    > example code piece:
    >
    > ENTITY car IS
    >
    >         PORT (
    >       RESET             : IN     std_logic;
    >                 CLK                     : IN     std_logic;
    >                 AutoInit        : IN     std_logic;
    >                 WriteDataIn     : IN     std_logic_vector( 7 DOWNTO 0);
    >                 BarData         : IN     std_logic_vector(15 DOWNTO 0);
    >                 UpdateAddr  : IN     std_logic_vector(15 DOWNTO 0);
    >                 LoadAddr    : IN     std_logic_vector( 1 DOWNTO 0);
    >                 EndOfDma                : IN     std_logic;
    >                 Update                  : IN     std_logic;
    >
    >                 CurrentAddr     : INOUT std_logic_vector(15 DOWNTO 0)
    >         );
    >
    > END car;
    >
    > --************************************************************************* *********************
    > -- Architecture Body
    > --************************************************************************* *********************
    >
    > ARCHITECTURE rtl OF car IS
    > BEGIN
    >
    >         writeadd: PROCESS ( LoadAddr, WriteDataIn, AutoInit, BarData, EndOfDma,
    >                                            Update, CurrentAddr, UpdateAddr, CLK, RESET )
    >
    >                 VARIABLE next_CurrentAddr : std_logic_vector(15 DOWNTO 0);
    >
    >         BEGIN
    >
    >                 IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    >                         next_CurrentAddr(7 DOWNTO 0) := BarData(7 DOWNTO 0);
    >
    >                 ELSIF (Update = '1') THEN
    >
    >                         next_CurrentAddr(7 DOWNTO 0) := UpdateAddr(7 DOWNTO 0);
    >
    >                 ELSIF (LoadAddr(0) = '1') THEN
    >
    >                         next_CurrentAddr(7 DOWNTO 0) := WriteDataIn(7 DOWNTO 0);
    >
    >                 ELSE
    >
    >                 next_CurrentAddr(7 DOWNTO 0) := CurrentAddr(7 DOWNTO 0);
    >
    >                 END IF;
    >
    >                 IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    >                         next_CurrentAddr(15 DOWNTO 8) := BarData(15 DOWNTO 8);
    >
    >                 ELSIF (Update = '1') THEN
    >
    >                         next_CurrentAddr(15 DOWNTO 8) := UpdateAddr(15 DOWNTO 8);
    >
    >                 ELSIF (LoadAddr(1) = '1') THEN
    >
    >                         next_CurrentAddr(15 DOWNTO 8) := WriteDataIn(7 DOWNTO 0);
    >
    >                 ELSE
    >
    >                         next_CurrentAddr(15 DOWNTO 8) := CurrentAddr(15 DOWNTO 8);
    >
    >                 END IF;
    >
    >                 IF ( RESET = '1' ) THEN         -- Asynchronous clear
    >
    >                         CurrentAddr(15 DOWNTO 0) <= "0000000000000000";
    >
    >                 ELSIF (CLK'EVENT AND (CLK = '0')) THEN
    >
    >                         CurrentAddr(15 DOWNTO 0) <= next_CurrentAddr(15 DOWNTO 0);
    >
    >                 END IF;
    >
    >         END PROCESS;
    >
    > END rtl;
    >
    > Kind regards
    > thomas_ns
    >
    > --
    > Message posted usinghttp://www.talkaboutprogramming.com/group/comp.lang.vhdl/
    > More information athttp://www.talkaboutprogramming.com/faq.html




    Check this link

    http://www.tek-tips.com/viewthread.cfm?qid=40899&page=1

    Verilog has a 'inout' port type apparently and it can be used as
    indicated in the above link.

    -Sudheendra Kadri
     
    sudhi, Dec 28, 2007
    #2
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  3. On Fri, 28 Dec 2007 11:01:55 -0600,
    thomas_ns <> wrote:

    > I have to transcode some project from VHDL to Verilog.
    > The problem is that I have some INOUT ports in VHDL code
    > which I can't just copy to Verilog code.
    > How can I do it?


    First, you can tell us what the blazes you think
    the inout ports in VHDL are doing. Right now they
    are permanently connected to the output of a bunch
    of flipflops, and are not "inout" at all - they
    are merely outputs. Some gorilla has used an INOUT
    port so that they can read back the output value into
    the logic. Fire that idiot, and learn how to do it
    properly in VHDL with an internal signal.

    In Verilog you can get exactly the same effect with
    a simple "output" port, which can be read back into
    the internal logic of a module without any special
    precautions.

    If you *really* need inouts in VHDL, to provide
    bidirectional ports with three-state outputs, then you
    can trivially translate that into Verilog. But you
    have not yet shown us why you might need that.

    Note that my comments apply only to synthesisable RTL
    designs. Testbench VHDL typically cannot be translated
    into Verilog without drastic restructuring.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Dec 28, 2007
    #3
  4. Jonathan is right. There is no need in the code you posted for the port to
    be INOUT. Probably the person that wrote the code got an error that the
    "CurrentAddr" had to be of type INOUT to be used on the right had
    expression. The original developer modified the code to get past the error
    message.

    If this is an old project and you are not allowed to change the port
    definitions you can do the following in verilog;

    inout [15:0] CurrentAddr;
    wire [15:0] CurrentAddr;
    reg [15:0] temp_CurrentAddr;

    assign CurrentAddr = temp_CurrentAddr;

    When you convert the procedures just use temp_currentAddr instead of
    CurrentAddr. This is how the original developer should have handled the
    error message in vhdl. Rather than change the port to INOUT, leave the port
    as OUT and create a signal temp_currentAddr std_logic_vector(15 downto 0);

    "thomas_ns" <> wrote in message
    news:...
    > Hello, everybody!
    >
    > I have to transcode some project from VHDL to Verilog.
    > The problem is that I have some INOUT ports in VHDL code which I can't
    > just copy to Verilog code.
    > How can I do it?
    >
    > example code piece:
    >
    > ENTITY car IS
    >
    > PORT (
    > RESET : IN std_logic;
    > CLK : IN std_logic;
    > AutoInit : IN std_logic;
    > WriteDataIn : IN std_logic_vector( 7 DOWNTO 0);
    > BarData : IN std_logic_vector(15 DOWNTO 0);
    > UpdateAddr : IN std_logic_vector(15 DOWNTO 0);
    > LoadAddr : IN std_logic_vector( 1 DOWNTO 0);
    > EndOfDma : IN std_logic;
    > Update : IN std_logic;
    >
    > CurrentAddr : INOUT std_logic_vector(15 DOWNTO 0)
    > );
    >
    > END car;
    >
    >
    > --**********************************************************************************************
    > -- Architecture Body
    > --**********************************************************************************************
    >
    > ARCHITECTURE rtl OF car IS
    > BEGIN
    >
    > writeadd: PROCESS ( LoadAddr, WriteDataIn, AutoInit, BarData, EndOfDma,
    > Update, CurrentAddr, UpdateAddr, CLK, RESET )
    >
    > VARIABLE next_CurrentAddr : std_logic_vector(15 DOWNTO 0);
    >
    > BEGIN
    >
    > IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := BarData(7 DOWNTO 0);
    >
    > ELSIF (Update = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := UpdateAddr(7 DOWNTO 0);
    >
    > ELSIF (LoadAddr(0) = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := WriteDataIn(7 DOWNTO 0);
    >
    > ELSE
    >
    > next_CurrentAddr(7 DOWNTO 0) := CurrentAddr(7 DOWNTO 0);
    >
    > END IF;
    >
    >
    > IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := BarData(15 DOWNTO 8);
    >
    > ELSIF (Update = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := UpdateAddr(15 DOWNTO 8);
    >
    > ELSIF (LoadAddr(1) = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := WriteDataIn(7 DOWNTO 0);
    >
    > ELSE
    >
    > next_CurrentAddr(15 DOWNTO 8) := CurrentAddr(15 DOWNTO 8);
    >
    > END IF;
    >
    > IF ( RESET = '1' ) THEN -- Asynchronous clear
    >
    > CurrentAddr(15 DOWNTO 0) <= "0000000000000000";
    >
    > ELSIF (CLK'EVENT AND (CLK = '0')) THEN
    >
    > CurrentAddr(15 DOWNTO 0) <= next_CurrentAddr(15 DOWNTO 0);
    >
    > END IF;
    >
    > END PROCESS;
    >
    > END rtl;
    >
    >
    >
    >
    > Kind regards
    > thomas_ns
    >
    > --
    > Message posted using
    > http://www.talkaboutprogramming.com/group/comp.lang.vhdl/
    > More information at http://www.talkaboutprogramming.com/faq.html
    >
     
    Dwayne Dilbeck, Jan 2, 2008
    #4
  5. thomas_ns

    Andy Guest

    On Dec 28 2007, 11:01 am, "thomas_ns" <> wrote:
    > Hello, everybody!
    >
    > I have to transcode some project from VHDL to Verilog.
    > The problem is that I have some INOUT ports in VHDL code which I can't
    > just copy to Verilog code.
    > How can I do it?
    >
    > example code piece:
    >
    > ENTITY car IS
    >
    > PORT (
    > RESET : IN std_logic;
    > CLK : IN std_logic;
    > AutoInit : IN std_logic;
    > WriteDataIn : IN std_logic_vector( 7 DOWNTO 0);
    > BarData : IN std_logic_vector(15 DOWNTO 0);
    > UpdateAddr : IN std_logic_vector(15 DOWNTO 0);
    > LoadAddr : IN std_logic_vector( 1 DOWNTO 0);
    > EndOfDma : IN std_logic;
    > Update : IN std_logic;
    >
    > CurrentAddr : INOUT std_logic_vector(15 DOWNTO 0)
    > );
    >
    > END car;
    >
    > --**********************************************************************************************
    > -- Architecture Body
    > --**********************************************************************************************
    >
    > ARCHITECTURE rtl OF car IS
    > BEGIN
    >
    > writeadd: PROCESS ( LoadAddr, WriteDataIn, AutoInit, BarData, EndOfDma,
    > Update, CurrentAddr, UpdateAddr, CLK, RESET )
    >
    > VARIABLE next_CurrentAddr : std_logic_vector(15 DOWNTO 0);
    >
    > BEGIN
    >
    > IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := BarData(7 DOWNTO 0);
    >
    > ELSIF (Update = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := UpdateAddr(7 DOWNTO 0);
    >
    > ELSIF (LoadAddr(0) = '1') THEN
    >
    > next_CurrentAddr(7 DOWNTO 0) := WriteDataIn(7 DOWNTO 0);
    >
    > ELSE
    >
    > next_CurrentAddr(7 DOWNTO 0) := CurrentAddr(7 DOWNTO 0);
    >
    > END IF;
    >
    > IF (AutoInit = '1') AND (EndOfDma = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := BarData(15 DOWNTO 8);
    >
    > ELSIF (Update = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := UpdateAddr(15 DOWNTO 8);
    >
    > ELSIF (LoadAddr(1) = '1') THEN
    >
    > next_CurrentAddr(15 DOWNTO 8) := WriteDataIn(7 DOWNTO 0);
    >
    > ELSE
    >
    > next_CurrentAddr(15 DOWNTO 8) := CurrentAddr(15 DOWNTO 8);
    >
    > END IF;
    >
    > IF ( RESET = '1' ) THEN -- Asynchronous clear
    >
    > CurrentAddr(15 DOWNTO 0) <= "0000000000000000";
    >
    > ELSIF (CLK'EVENT AND (CLK = '0')) THEN
    >
    > CurrentAddr(15 DOWNTO 0) <= next_CurrentAddr(15 DOWNTO 0);
    >
    > END IF;
    >
    > END PROCESS;
    >
    > END rtl;
    >
    > Kind regards
    > thomas_ns
    >
    > --
    > Message posted usinghttp://www.talkaboutprogramming.com/group/comp.lang.vhdl/
    > More information athttp://www.talkaboutprogramming.com/faq.html


    Ouch! who wrote that code?

    Perhaps this will help:

    writeadd: process (reset, clk) is
    begin
    if reset = '1' then
    CurrentAddr <= (others => '0');
    elsif rising_edge(clk) then
    IF (AutoInit AND EndOfDma) = '1' THEN
    CurrentAddr <= BarData;
    ELSIF Update = '1' THEN
    CurrentAddr <= UpdateAddr;
    ELSE
    IF LoadAddr(0) = '1' THEN
    CurrentAddr(7 DOWNTO 0) <= WriteDataIn;
    END IF;
    IF LoadAddr(1) = '1' THEN
    CurrentAddr(15 DOWNTO 8) <= WriteDataIn;
    END IF;
    END IF:
    end if;
    end process writeadd;

    No inout ports required...

    Andy
     
    Andy, Jan 3, 2008
    #5
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