vhdl and ultraedit

Discussion in 'VHDL' started by mans, Apr 23, 2007.

  1. mans

    mans Guest

    Hello,
    I decided to test UltraEdit to see how good is it in reformatting a
    VHDL code and indenting smartly. To do this I installed ultraedit and I did
    a test by asking UE to reformat this code for me:


    process (Rst)
    begin
    if clk='1' then

    if Rst='1' then system_state <= wait_for_input;

    end if;
    end if;
    end process;

    and I got this:

    process (Rst) begin if clk='1' then

    if Rst='1' then system_state <= wait_for_input;

    end if; end if; end process;

    which I think is not a good reformatting.

    My question is:

    Can UE reformat VHDL code and doing the smart indentation on it?
    Is the result that I am getting correct?
    Am I missing anything?
    My search on the web showed that I should get a new file for this, Am I
    right? Where can I get it?

    Regards
     
    mans, Apr 23, 2007
    #1
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