VHDL code error

[suraj lulla]

hi i am getting the following error. eventhough the actuals n formals
total to the same.

entity fouradd is
Port ( A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
B0 : in STD_LOGIC;
B1 : in STD_LOGIC;
B2 : in STD_LOGIC;
B3 : in STD_LOGIC;
cin : in STD_LOGIC;

S0 : out STD_LOGIC;
S1 : out STD_LOGIC;
S2 : out STD_LOGIC;
S3 : out STD_LOGIC;
cout : out STD_LOGIC);
end fouradd;



u5:component fouradd port
map(s0(0),s0(1),s0(2),s0(3),s1(0),s1(1),s1(2),s1(3),o(0),s4(0),s4(1),s4(2),s4(3),s4(4));

 

[backhus]

hi i am getting the following error. eventhough the actuals n formals
total to the same.

entity fouradd is
    Port ( A0 : in  STD_LOGIC;
                                A1 : in  STD_LOGIC;
                                A2 : in  STD_LOGIC;
                                A3 : in  STD_LOGIC;
           B0 : in  STD_LOGIC;
                          B1 : in  STD_LOGIC;
                          B2 : in  STD_LOGIC;
                          B3 : in  STD_LOGIC;
           cin : in  STD_LOGIC;

           S0 : out  STD_LOGIC;
                          S1 : out  STD_LOGIC;
                          S2 : out  STD_LOGIC;
                          S3 : out  STD_LOGIC;
                          cout : out  STD_LOGIC);
end fouradd;

u5:component fouradd port
map(s0(0),s0(1),s0(2),s0(3),s1(0),s1(1),s1(2),s1(3),o(0),s4(0),s4(1),s4(2),s4(3),s4(4));

Hi,
so, which error do you get? you forgot to mention.

Besides the missing librariy and use statements, have you heared about
std_logic_vectors?
e.g. A : in std_logic_vector(3 downto 0);

You can eiter declare a component or instantiate it.
A component declaration has no port map, but a port declaration like
an entity.
An instance can be made without a component declaration. This is
called an inline instantiation.
e.g. u5:entity work.fouradd(arc_name)
port
map(s0(0),s0(1),s0(2),s0(3),s1(0),s1(1),s1(2),s1(3),o(0),s4(0),s4(1),s4(2),s4(3),s4(4));

You should prefer named associations instead of positional.
A little more writing, that can be automatized but less error prone
and better to maintain.

Have a nice synthesis
Eilert