VHDL CODE....Please Check....

Discussion in 'VHDL' started by falconite, Mar 30, 2010.

  1. falconite

    falconite

    Joined:
    Mar 30, 2010
    Messages:
    1
    Heya....i want to implement a 8 bit binary counter....will the following code work???I dont hav access to the s/w n so cant check myself....

    library ieee;
    use ieee.std_logic_1164.all;

    entity counter is
    port(CLK,RST:IN std_logic;
    Q,QN:OUT std_logic_vector(7 downto 0));
    end counter;

    architecture arch of counter is
    begin
    process(CLK,RST)
    begin
    if(RST='0')
    then Q<="00000000";
    elsif (CLK='1' and CLK'event)
    then Q=Q+;
    end if;
    end process;
    QN<=not Q;
    end arch;

    RST is low enable and the counter is +ve edge triggered.....
     
    falconite, Mar 30, 2010
    #1
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  2. falconite

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    [COLOR="Sienna"]use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;[/COLOR]
    
    entity counter is
        port(CLK,RST:IN std_logic;
        Q,QN:OUT std_logic_vector(7 downto 0));
    end counter;
    
    architecture arch of counter is
        [COLOR="sienna"]signal Qtemp: std_logic_vector(7 downto 0);[/COLOR]
    begin
        process(CLK,RST)
        begin
            if(RST='0')
                then Qtemp<="00000000";
                elsif (CLK='1' and CLK'event)
                then Qtemp=Qtemp+[COLOR="sienna"]1[/COLOR];
           end if;
         end process;
        [COLOR="sienna"]Q  <= Qtemp;[/COLOR]
        QN<=not Qtemp;
    end arch;
    This more likely to work - an alternative to Qtemp could be the INOUT attribute.
    You need the extra libraries in order to perform the +1

    your welcome
     
    Last edited: Mar 31, 2010
    jeppe, Mar 31, 2010
    #2
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