VHDL language of choice?

[Tim Hubberstey]

Hi Tim,

I came from a hardware background and found
it odd when first maintaining a C program that I had to
wade through a nest of #ifndefs and hack
some #defines to get the options right.
Maintaining the *almost* C-like macros
can also be challenging for a bit bouncer.

Unfortunately, any language feature can be abused. I also come from a
hardware background so I understand what you mean. However, a lot of the
pre-processor complexity you see in C code often comes from people
writing code that will work on many different platforms and operating
systems.

If it's my code, I am inclined to just edit in the change
and use version control to dig it up if I ever have to.
If it's an untouchable entity, I can make a wrapper
in about a minute.

That's fine, as long as you're the only person dealing with the code. I
try to write code that is, as much as possible, reusable and
parameterizable. This often results in situations where you want to vary
the port list to include/exclude control signals. There are ways you can
do this that stay within the existing VHDL definition, but these methods
often result in compiler and/or synthesis warnings that add confusion to
the log files. Using a pre-processor, IMO, produces much cleaner results
for the *user* of an IP block even though the code inside the block may
be a little harder to understand.

I prefer to keep my code free of directives and
make those settings in the back-end files.

This is, mostly, a style issue so I won't disagree with your choice.
However, there are some pragmas that *must* be inside the code because
the tool the pragma is for doesn't have any back-end files. Some code
coverage and formal verification tools come to mind here.

Even if you don't choose to intentionally use pragmas in your code, it
can still happen by accident. For instance, I once wasted an entire
day's synthesis run because I reformatted a comment block and
inadvertently ended up with a comment line that started out:
-- Synopsys ...
This caused the synthesis of the block to fail which, since it was a
block instantiated by many other blocks, caused the entire 18-hour
synthesis run to fail.

Even worse is the case where you accidentally generate a valid pragma
that causes some subtle error in your result. My point is that, whether
you choose to use them or not, pragmas have no business looking like
comments.

 

[Tim Hubberstey]

Do we need a preprocessor, if something like the generate statements
would be extended to the signal declaration and to the entity? Such a
solution would offer configuration using one idea - not two like the
parameter and defines in Verilog.

Possibly not for pre-processing, as long as the pragma issue is
addressed somehow.

However, I would still like to see a macro capability. Generates are
powerful and can do many things, but sometimes they either just aren't
enough (lack of an "else" clause is a big failing), or are way too complex.

 

[Mike Treseler]

However, there are some pragmas that *must* be inside the code because
the tool the pragma is for doesn't have any back-end files. Some code
coverage and formal verification tools come to mind here.

Thanks for the tip. I will remind myself
not to bother evaluating such tools.
Modelsim seems to do ok on
code coverage without resorting to such hacks.

-- Synopsys ...
This caused the synthesis of the block to fail which, since it was a
block instantiated by many other blocks, caused the entire 18-hour
synthesis run to fail.

Serious bummer. I'll resolve to keep vendor names
and keywords like "translate" out of my comments.

My point is that, whether
you choose to use them or not, pragmas have no business looking like
comments.

I agree that comments ought to be ignored by all tools.
Some of the vendors use vhdl attributes to do this sort of thing.
At least that eliminates the possible side effects of putting
vendor settings in source code.


-- Mike Treseler

 

[Tim Hubberstey]

I used to think that vhdl would be more readable than verilog, but I've
seen too much vhdl code that looks like this:

x := std_logic_vector(to_unsigned((to_integer(unsigned(z1)) +
to_integer(unsigned(z2))), 9));
y := std_logic_vector(to_unsigned((to_integer(unsigned(x(7
DOWNTO 0))) + to_integer(unsigned(x(8
DOWNTO 8)))), 8));

This really an issue with the standard packages and not the language
itself (a hairline distinction). Many people create their own packages
that crunch this kind of thing down to something reasonable. For
instance, I use a function, AddSLV(vec_1, vec_2, mode), that takes 2
standard_logic_vectors and "adds" them. The "add" function can be signed
or unsigned 2's complement, Gray, etc. as defined by the mode value.

which I *think* is meant to do the same thing as this nice verilog
code:

x = z1 + z2;
y = x[7:0] + x[8];

You could write the exact equivalent in VHDL by using the unsigned
package instead of the numeric_bit package:

x <= z1 + z2;
y <= x(7 downto 0) + x(8);
^-- not sure about this since I don't use the
unsigned package. Might need to re-size it.

(Now try to imagine the above vhdl code with really long identifiers
instead of the short identifiers that I used.)

Some vhdl proponents believe that readability is synonymous with
verbosity.

No argument there. I much prefer the [x:y] notation to (x downto y).
It's also a safe bet that something that basic is never going to change.

However, your example isn't really about readability -- it's about
strong (VHDL) vs weak (Verilog) typing. Some people like a
strongly-typed language because of the implicit error checking, others
hate it because the typing "keeps me from doing what I want". It's a
philosophical difference that goes much deeper than just syntax and is
probably just as religious as Mac vs PC or Linux vs Windows.

 

[Jim Lewis]

-- Warning! Rant_Mode <= true

The problem with this method is that there are some issues that the
language controllers are simply not willing to address.

I think for future revisions of VHDL all user requests
need to be on the table. To get a good solution, we
need to get many perspectives. One of the challenges
is to translate from a request that suggests an
implementation to the underlying requirement - because
there may be a better way of addressing the requirement
that is already being proposed.

The original language designers have blessed us with a
clean, consistent language. As we move forward, those of
us who decide to answer the call and step into this role,
need to work hard to keep the language clean and consistent.

Don't get discouraged because something was rejected in the
past, however, do keep in mind the rule about standards:

With standards you don't necessarily get what you want,
but you usually will get something you can live with.


Just so you understand the process we are currently are
using (and may become the model for future revisions):
things that are high value and someone is interested
in working on will get worked on. Keep in mind that they
will have to be traded off between other potential candidate
solutions. So far this seems to have been working well.

If you don't have alot of time, working on just one proposal
that has high value to you is great. If you don't feel
up to working on language proposals, even being aware of
what we are doing and telling your vendors which proposals
are of high value to you will ensure that your vendors take
note and start consider how they are going to implement
the features.

Beyond language proposals, if you look at the big differences
between the capability of "C" and VHDL, you will note that it
is not in the langauge capability, but the fact that C has
an extensive number of libraries. VHDL has some ground to
cover with respect to implementing packages.

Again, if you don't feel up to writing these sort of things,
we will need people who try them out. Make sure the use
model is ok. Test them and find bugs.

There is plenty to do. As we finish the fast track phase and
move to the next phase, we are going to need to do more planning.
Once that planning is complete, we will be able to be more
specific about what needs to be done.

Beyond this, while most WG activities are done on a voluntary
basis, LRM editing is a paid position and we need between
$100K and $150K to finish fast track edits. If you know of
an organization who is willing to help us reach our goal,
please let myself or Steve Bailey (VASG Chair) know. Please
note that neither IEEE dues nor IEEE-SA dues nor donations
to IEEE-SA go to fund IEEE standards working groups. Only
donated directly to the working group funding organization
goes to the working group.


Best Regards,
Jim Lewis
VASG Vice Chair
VHDL-200X Fast Track Co-Team lead
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

Tim Hubberstey wrote:




Do we need a preprocessor, if something like the generate statements
would be extended to the signal declaration and to the entity? Such a
solution would offer configuration using one idea - not two like the
parameter and defines in Verilog.


Ralf

On a similar note, is there another answer for paramterizing
entity interfaces such as introducing some type of interface
abstraction.

---

BTW, the way I currently handle entities is to define all of
the signals. For designs that don't need some of the IO, I
tie off the inputs to constants and leave outputs open.
For FPGA tools this seems to be enough.

For ASIC tools, I instantiate the block inside of another block
with the only the IO I need and then during synthesis, remove
the level of hierarchy for the re-usable component. The result
is a single component without any unused IO. A few more tool
steps but it gets the job done.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

Tim,

Possibly not for pre-processing, as long as the pragma issue is
addressed somehow.

Very few of the synthesis tool pragmas made it into 1076.6
(the VHDL RTL Synthesis Standard). Instead 1076.6 mostly
uses attributes.

Unfortunately, there is nothing a standards organization can
do to prevent tool vendors from doing their own things that
are outside of the language. So I think WRT pragmas, we are
stuck. Perhaps what you need is a switch or configuration for
your synthesis tool that says don't do pragmas or only do IEEE
standard pragmas. With this said, you would have to convince
your tool vendor that it is worthy for them to spend the money
to implement this feature.

If you want more standard attributes in standard IEEE 1076.6,
talk to your tool vendors and tell them the importantance
of standards and ask them to join the 1076.6 working group
(and get them to kick off the next revision of the standard).

However, I would still like to see a macro capability. Generates are
powerful and can do many things, but sometimes they either just aren't
enough (lack of an "else" clause is a big failing), or are way too complex.

We considered this for VHDL-200X fast track, but decided
it is more complex than we wanted to tackle in that revision.
The problem is that every branch through a if/else
generate or case generate would need to create an
independently named block (that can be referenced in
a configuration). Going further should each branch also
have a separate declarative region? There is no reason
that this cannot be worked on in the next phase of
VHDL-200X. The only thing we need is for someone to step
forward who wants to work on it.

I have a number of things I personally want to spend time
on in the next revision. This one unfortunately does not
make my list. Not because it is not worthy - but instead
because there are other things that have higher value to me
(and I am selfish).

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~