vhdl random numbers from a text

Discussion in 'VHDL' started by ziggi, Feb 14, 2011.

  1. ziggi

    ziggi

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    Hi.

    Just curious to know if its all possible with vhdl to load a bunch of random numbers generated by some program into vhdl, and then produce a signal as output from these random numbers. Im trying to do this but I run into problems regarding the size of the array, and also the signal produced is not random at all....

    Does anyone have any ideas on this.?
     
    ziggi, Feb 14, 2011
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  2. ziggi

    SystemVerilog

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    You can use my LFSR package to produce pseudo random numbers. Note that in the LFSR the numbers do not repeat until the sequence is exhausted.
    See my site ( SystemVerilog dot us ) under LINKS VHDL_MODEL

    If you could use SystemVerilog in mixed mode, you would have more versatility because you can define random numbers with constraints.
    --------------------------------------------------------------------------
    Ben Cohen
    * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
    * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
    * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
    * Component Design by Example, 2001 ISBN 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
    --------------------------------------------------------------------------
     
    SystemVerilog, Feb 15, 2011
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