VHDL statement execution order

[mreister]

Ok, I am still learning VHDL and I am having some problems with execution order of statements. Take for example the following code:

entity add_w_carry is
port(
a,b: in std_logic_vector(3 downto 0);
cout: out std_logic;
sum: out std_logic_vector(3 downto 0);
);
end add_w_carry;


architecture hard_arch of add_w_carry is
signal a_ext, b_ext,sum_ext: unsigned(4 downto 0);

begin
a_ext <= unsigned('0' & a);
b_ext <= unsigned('0' & b);
sum_ext <= a_ext + b_ext;
end hard_arch

Now I know this code is suppose to take the input a,b and extended them by one bit then add them together. But where I am a little fuzzy is the order in which this happens. I thought since this is a combinational circuit all these statements execute in parallel but this would mean that the addition would happen before a_ext and b_ext where evaluated. Obviously its suppose to evaluate a_ext and b_ext first but how do the synthesis tools know to evaluate this statement in the correct order? What if I wanted all three statements to execute in parallel?

 

[jeppe]

Well - talking about concurrent statements (as in your example). They will be executed in the order they are needed when they are needed.

In contrast will the statements inside a process be executed in the order they are writen (like a computerprogram).

Search the net for the interactive book: "Evita VHDL" - chapter 6 + 7 will explain it all.

Jeppe