Vhdl syntax for generate ...

Discussion in 'VHDL' started by olivier90dir@gmail.com, Jan 31, 2013.

  1. Guest

    Hi all ,

    I have a question
    I would like the equivalent of this code : A<=B(0) or B(1) or B(2) or ... B(N). with loop generate.

    I tired this code :
    CevRec: for Ilink in 0 to NB_FLT-1 generate
    A <= A or B(Ilink);
    end generate CevRec;
    result <= A ;
    remark A is an signal.
    At the compilation I have an error :
    Multiple non-tristate drivers for net ...

    Thank for yor help .

    Oliver
     
    , Jan 31, 2013
    #1
    1. Advertising

  2. Rob Gaddi Guest

    On Thu, 31 Jan 2013 08:25:56 -0800 (PST)
    wrote:

    > Hi all ,
    >
    > I have a question
    > I would like the equivalent of this code : A<=B(0) or B(1) or B(2) or ... B(N). with loop generate.
    >
    > I tired this code :
    > CevRec: for Ilink in 0 to NB_FLT-1 generate
    > A <= A or B(Ilink);
    > end generate CevRec;
    > result <= A ;
    > remark A is an signal.
    > At the compilation I have an error :
    > Multiple non-tristate drivers for net ...
    >
    > Thank for yor help .
    >
    > Oliver
    >
    >


    Can't do that with a signal, and therefore you can't do it with a
    for..generate loop. If your synthesis tool supports VHDL-2008, there's
    a unary OR operator. If not, bring in the std_logic_misc library, and
    use the OR_REDUCE function. Or you could write your own OR_REDUCE with
    a for..loop, using a variable instead of a signal, which will work. But
    either way, you want:

    result <= or B; (VHDL-2008)
    result <= OR_REDUCE(B); (earlier)


    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.
     
    Rob Gaddi, Jan 31, 2013
    #2
    1. Advertising

  3. rickman Guest

    On 1/31/2013 12:05 PM, Rob Gaddi wrote:
    > On Thu, 31 Jan 2013 08:25:56 -0800 (PST)
    > wrote:
    >
    >> Hi all ,
    >>
    >> I have a question
    >> I would like the equivalent of this code : A<=B(0) or B(1) or B(2) or ... B(N). with loop generate.
    >>
    >> I tired this code :
    >> CevRec: for Ilink in 0 to NB_FLT-1 generate
    >> A<= A or B(Ilink);
    >> end generate CevRec;
    >> result<= A ;
    >> remark A is an signal.
    >> At the compilation I have an error :
    >> Multiple non-tristate drivers for net ...
    >>
    >> Thank for yor help .
    >>
    >> Oliver
    >>
    >>

    >
    > Can't do that with a signal, and therefore you can't do it with a
    > for..generate loop. If your synthesis tool supports VHDL-2008, there's
    > a unary OR operator. If not, bring in the std_logic_misc library, and
    > use the OR_REDUCE function. Or you could write your own OR_REDUCE with
    > a for..loop, using a variable instead of a signal, which will work. But
    > either way, you want:
    >
    > result<= or B; (VHDL-2008)
    > result<= OR_REDUCE(B); (earlier)


    The loop should work just fine if a variable is added, then assigned to
    the signal at the end of the loop. No need for the generate statement,
    but it would need to be in a process or a function. In fact, this would
    make a good function... which is what has been done in VHDL-2008 with
    the uniary operators.

    variable temp : std_logic;

    TestCode: for Ilink in 0 to NB_FLT-1 loop
    temp := temp or B(Ilink);
    end loop;
    A <= temp;

    I've been using VHDL-2008 on my latest project and it is working well.
    My only issue is finding good documentation I can use offline. I would
    buy an e-book if I knew any given one was a good one.

    --

    Rick
     
    rickman, Jan 31, 2013
    #3
  4. Guest

    > variable temp : std_logic;
    >
    > TestCode: for Ilink in 0 to NB_FLT-1 loop
    > temp := temp or B(Ilink);
    > end loop;
    > A <= temp;


    Don't forget to initialize the variable!
     
    , Jan 31, 2013
    #4
  5. rickman Guest

    On 1/31/2013 5:35 PM, wrote:
    >> variable temp : std_logic;
    >>
    >> TestCode: for Ilink in 0 to NB_FLT-1 loop
    >> temp := temp or B(Ilink);
    >> end loop;
    >> A<= temp;

    >
    > Don't forget to initialize the variable!


    Very good point. Does this do it? I'm pretty sure that unlike signals
    where initialization is not always supported in synthesis, variable
    initialization should be ok.


    variable temp : std_logic := '0';

    TestCode: for Ilink in 0 to NB_FLT-1 loop
    temp := temp or B(Ilink);
    end loop;
    A<= temp;

    --

    Rick
     
    rickman, Jan 31, 2013
    #5
  6. Guest

    Le vendredi 1 février 2013 00:44:25 UTC+1, rickman a écrit :
    > On 1/31/2013 5:35 PM, wrote:
    >
    > >> variable temp : std_logic;

    >
    > >>

    >
    > >> TestCode: for Ilink in 0 to NB_FLT-1 loop

    >
    > >> temp := temp or B(Ilink);

    >
    > >> end loop;

    >
    > >> A<= temp;

    >
    > >

    >
    > > Don't forget to initialize the variable!

    >
    >
    >
    > Very good point. Does this do it? I'm pretty sure that unlike signals
    >
    > where initialization is not always supported in synthesis, variable
    >
    > initialization should be ok.
    >
    >
    >
    >
    >
    > variable temp : std_logic := '0';
    >
    >
    >
    > TestCode: for Ilink in 0 to NB_FLT-1 loop
    >
    > temp := temp or B(Ilink);
    >
    > end loop;
    >
    > A<= temp;
    >
    >
    >
    > --
    >
    >
    >
    > Rick

    Thank For your Help ...

    olive.
     
    , Feb 1, 2013
    #6
  7. Andy Guest

    Synthesis supports declaration initializations in subprograms (functions orprocedures). Some FPGA synthesis tools will support declaration initializations in processes for some targets, but using them is fraught with all kinds of problems (it involves the system reset, which is best handled explicitly for a variety of reasons beyond the scope of this discussion)

    Whether it will do what you need, that depends...

    If this code is enclosed in a subprogram that is called inside a process, then the variable gets initialized each time the subprogram is called, and it will do what you need.

    However, if this code is embedded directly inside a process, the variable initialization happens only once, when the process is initialized. The process never exits, it only suspends and wakes up again, executing only the executable statements until it suspends again (declarations are not consideredexecutable statements, even if they execute a subprogram call in an initialization). Therefore, the variable is only initialized once, and will not work in this application. You would need an assignment statement prior to the loop to initialize the variable every time before the loop runs.

    Andy
     
    Andy, Feb 4, 2013
    #7
  8. rickman Guest

    On 2/4/2013 11:50 AM, Andy wrote:
    > Synthesis supports declaration initializations in subprograms (functions or procedures). Some FPGA synthesis tools will support declaration initializations in processes for some targets, but using them is fraught with all kinds of problems (it involves the system reset, which is best handled explicitly for a variety of reasons beyond the scope of this discussion)
    >
    > Whether it will do what you need, that depends...
    >
    > If this code is enclosed in a subprogram that is called inside a process, then the variable gets initialized each time the subprogram is called, and it will do what you need.
    >
    > However, if this code is embedded directly inside a process, the variable initialization happens only once, when the process is initialized. The process never exits, it only suspends and wakes up again, executing only the executable statements until it suspends again (declarations are not considered executable statements, even if they execute a subprogram call in an initialization). Therefore, the variable is only initialized once, and will not work in this application. You would need an assignment statement prior to the loop to initialize the variable every time before the loop runs.
    >
    > Andy


    Yep, I gave the process a test and you are absolutely right, the
    variable only gets initialized once when the process is initialized.

    --

    Rick
     
    rickman, Feb 6, 2013
    #8
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Weng Tianxiang
    Replies:
    5
    Views:
    1,318
    Christophe
    Feb 16, 2006
  2. Mikael Petterson

    xsl syntax to generate all caps with _

    Mikael Petterson, Sep 10, 2003, in forum: XML
    Replies:
    3
    Views:
    916
    Dimitre Novatchev
    Sep 11, 2003
  3. Replies:
    3
    Views:
    416
    red floyd
    Apr 7, 2006
  4. afd
    Replies:
    1
    Views:
    8,365
    Colin Paul Gloster
    Mar 23, 2007
  5. Harlan Messinger
    Replies:
    2
    Views:
    2,306
    John Bell
    Mar 28, 2010
Loading...

Share This Page