VHDL / SystemC Cosimulation problem

Discussion in 'VHDL' started by manu, Apr 5, 2006.

  1. manu

    manu Guest

    Hi,
    I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
    design.
    All my synthesisable modules are written in VHDL and all my test benches
    are written in SystemC since it offers very convenient features to build
    complex test scenarios.
    Until Now, it was OK since all my VHDL modules had "trivial" data types
    on their ports (eg. std_logic and std_logic_vector). So the generation
    of SystemC wrappers for my HDL modules was very easy thank to
    "scgenmod" command.
    Now, I want to use a custom data type like the following one :

    package mytypes is
    type my_custom_type_t is record
    my_flag : std_logic;
    my_bus : std_logic_vector(WIDTH-1 downto 0);
    more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    ...
    end record;
    end package;

    and for my entity :

    entity mydesign_top is
    port
    (
    custom_input : in my_custom_type_t;

    ...All my other stuff...
    );
    end mydesign_top;

    The problem is I don't know any "smart" way to bind a SytemC type to my
    custom VHDL type. The only workaround I found for the moment is to
    encapsulate my VHDL module into a VHDL wrapper in which I perform a
    breakout of my custom type :

    entity mydesign_top_wrap is
    port
    (
    --begin custom_input breakout
    custom_input_flag : std_logic;
    custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
    custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    ...
    --end custom_input breakout

    ...All my other stuff...
    );
    end mydesign_top_wrap;

    But I don't like this solution because it is very hard to maintain my
    whole source code when I modify the definition of my_custom_type_t.
    Idealy, I would like to have only two file to modify : the VHDL package
    and a corresponding C++ header in which would be defined the type mapping.
    Does anyone know how to do this or any clean workaround ?
    thanks for your help !

    Manu
     
    manu, Apr 5, 2006
    #1
    1. Advertising

  2. manu wrote:

    > All my synthesisable modules are written in VHDL and all my test benches
    > are written in SystemC since it offers very convenient features to build
    > complex test scenarios.

    ....
    > The problem is I don't know any "smart" way to bind a SytemC type to my
    > custom VHDL type. The only workaround I found for the moment is to
    > encapsulate my VHDL module into a VHDL wrapper in which I perform a
    > breakout of my custom type :


    I prefer to make all my top ports
    std_logic_vectors and
    std_ulogic bits because these types
    are support by all tools and all designers.

    I declare my_custom_types_t inside
    the top architecture. Most of the real wide,
    interesting structures are inside anyway.

    -- Mike Treseler
     
    Mike Treseler, Apr 5, 2006
    #2
    1. Advertising

  3. manu

    Hans Guest

    Hi Manu,

    Interesting question. I suspect that this is not possible given the
    restriction of only supporting locally static subtypes and arrays. However,
    I would suggest you pass this on to Mentor support and see what they come
    back with. You might also want to try the OSCI SystemC newsgroup. If you
    find a solution please post it here and/or send me an email since I am also
    interested in this.

    Hans
    www.ht-lab.com




    "manu" <> wrote in message
    news:44342e94$0$27279$...
    > Hi,
    > I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
    > design.
    > All my synthesisable modules are written in VHDL and all my test benches
    > are written in SystemC since it offers very convenient features to build
    > complex test scenarios.
    > Until Now, it was OK since all my VHDL modules had "trivial" data types on
    > their ports (eg. std_logic and std_logic_vector). So the generation of
    > SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
    > command.
    > Now, I want to use a custom data type like the following one :
    >
    > package mytypes is
    > type my_custom_type_t is record
    > my_flag : std_logic;
    > my_bus : std_logic_vector(WIDTH-1 downto 0);
    > more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    > ...
    > end record;
    > end package;
    >
    > and for my entity :
    >
    > entity mydesign_top is
    > port
    > (
    > custom_input : in my_custom_type_t;
    >
    > ...All my other stuff...
    > );
    > end mydesign_top;
    >
    > The problem is I don't know any "smart" way to bind a SytemC type to my
    > custom VHDL type. The only workaround I found for the moment is to
    > encapsulate my VHDL module into a VHDL wrapper in which I perform a
    > breakout of my custom type :
    >
    > entity mydesign_top_wrap is
    > port
    > (
    > --begin custom_input breakout
    > custom_input_flag : std_logic;
    > custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
    > custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    > ...
    > --end custom_input breakout
    >
    > ...All my other stuff...
    > );
    > end mydesign_top_wrap;
    >
    > But I don't like this solution because it is very hard to maintain my
    > whole source code when I modify the definition of my_custom_type_t.
    > Idealy, I would like to have only two file to modify : the VHDL package
    > and a corresponding C++ header in which would be defined the type mapping.
    > Does anyone know how to do this or any clean workaround ?
    > thanks for your help !
    >
    > Manu
     
    Hans, Apr 6, 2006
    #3
  4. manu

    Stephane Guest

    Hi Manu!

    I asked my fellow here and they said "hummm... you'll have to wrap it"!

    anyway, maybe the following functions may help:
    mti_GetNumRecordElements
    mti_GetSignalSubelements
    and so on...

    the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/

    and also an example is
    <modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
    (this one is pure C)

    HTH and that we'll have a beer together one of these days!
    Stephane

    manu wrote:
    > Hi,
    > I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
    > design.
    > All my synthesisable modules are written in VHDL and all my test benches
    > are written in SystemC since it offers very convenient features to build
    > complex test scenarios.
    > Until Now, it was OK since all my VHDL modules had "trivial" data types
    > on their ports (eg. std_logic and std_logic_vector). So the generation
    > of SystemC wrappers for my HDL modules was very easy thank to
    > "scgenmod" command.
    > Now, I want to use a custom data type like the following one :
    >
    > package mytypes is
    > type my_custom_type_t is record
    > my_flag : std_logic;
    > my_bus : std_logic_vector(WIDTH-1 downto 0);
    > more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    > ...
    > end record;
    > end package;
    >
    > and for my entity :
    >
    > entity mydesign_top is
    > port
    > (
    > custom_input : in my_custom_type_t;
    >
    > ...All my other stuff...
    > );
    > end mydesign_top;
    >
    > The problem is I don't know any "smart" way to bind a SytemC type to my
    > custom VHDL type. The only workaround I found for the moment is to
    > encapsulate my VHDL module into a VHDL wrapper in which I perform a
    > breakout of my custom type :
    >
    > entity mydesign_top_wrap is
    > port
    > (
    > --begin custom_input breakout
    > custom_input_flag : std_logic;
    > custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
    > custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    > ...
    > --end custom_input breakout
    >
    > ...All my other stuff...
    > );
    > end mydesign_top_wrap;
    >
    > But I don't like this solution because it is very hard to maintain my
    > whole source code when I modify the definition of my_custom_type_t.
    > Idealy, I would like to have only two file to modify : the VHDL package
    > and a corresponding C++ header in which would be defined the type mapping.
    > Does anyone know how to do this or any clean workaround ?
    > thanks for your help !
    >
    > Manu
     
    Stephane, Apr 6, 2006
    #4
  5. manu

    Hans Guest

    I might be wrong but I don't think the FLI interface is going to help him.
    The VHDL/SystemC interface of Modelsim is very easy, adding an FLI layer
    will make it far too complex and less portable IMHO. Perhaps the wrapper is
    the only solution.....?

    Hans
    www.ht-lab.com


    "Stephane" <> wrote in message
    news:e13f8h$93c$...
    > Hi Manu!
    >
    > I asked my fellow here and they said "hummm... you'll have to wrap it"!
    >
    > anyway, maybe the following functions may help:
    > mti_GetNumRecordElements
    > mti_GetSignalSubelements
    > and so on...
    >
    > the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/
    >
    > and also an example is
    > <modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
    > (this one is pure C)
    >
    > HTH and that we'll have a beer together one of these days!
    > Stephane
    >
    > manu wrote:
    >> Hi,
    >> I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
    >> design.
    >> All my synthesisable modules are written in VHDL and all my test benches
    >> are written in SystemC since it offers very convenient features to build
    >> complex test scenarios.
    >> Until Now, it was OK since all my VHDL modules had "trivial" data types
    >> on their ports (eg. std_logic and std_logic_vector). So the generation of
    >> SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
    >> command.
    >> Now, I want to use a custom data type like the following one :
    >>
    >> package mytypes is
    >> type my_custom_type_t is record
    >> my_flag : std_logic;
    >> my_bus : std_logic_vector(WIDTH-1 downto 0);
    >> more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    >> ...
    >> end record;
    >> end package;
    >>
    >> and for my entity :
    >>
    >> entity mydesign_top is
    >> port
    >> (
    >> custom_input : in my_custom_type_t;
    >>
    >> ...All my other stuff...
    >> );
    >> end mydesign_top;
    >>
    >> The problem is I don't know any "smart" way to bind a SytemC type to my
    >> custom VHDL type. The only workaround I found for the moment is to
    >> encapsulate my VHDL module into a VHDL wrapper in which I perform a
    >> breakout of my custom type :
    >>
    >> entity mydesign_top_wrap is
    >> port
    >> (
    >> --begin custom_input breakout
    >> custom_input_flag : std_logic;
    >> custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
    >> custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    >> ...
    >> --end custom_input breakout
    >>
    >> ...All my other stuff...
    >> );
    >> end mydesign_top_wrap;
    >>
    >> But I don't like this solution because it is very hard to maintain my
    >> whole source code when I modify the definition of my_custom_type_t.
    >> Idealy, I would like to have only two file to modify : the VHDL package
    >> and a corresponding C++ header in which would be defined the type
    >> mapping.
    >> Does anyone know how to do this or any clean workaround ?
    >> thanks for your help !
    >>
    >> Manu
     
    Hans, Apr 6, 2006
    #5
  6. manu

    manu Guest

    Hi Stephane,
    I agree with Hans. Actually I really don't like the FLI and if I had to
    choose, I prefer the initial VHDL wrapper solution.
    I will post this topic on SystemC mailing list too and get in touch with
    Mentor support.
    Answer(s) in the next post (I hope...).

    Manu

    PS : And for the beer, I hope too ! ;-)

    Hans a écrit :
    > I might be wrong but I don't think the FLI interface is going to help him.
    > The VHDL/SystemC interface of Modelsim is very easy, adding an FLI layer
    > will make it far too complex and less portable IMHO. Perhaps the wrapper is
    > the only solution.....?
    >
    > Hans
    > www.ht-lab.com
    >
    >
    > "Stephane" <> wrote in message
    > news:e13f8h$93c$...
    >
    >>Hi Manu!
    >>
    >>I asked my fellow here and they said "hummm... you'll have to wrap it"!
    >>
    >>anyway, maybe the following functions may help:
    >>mti_GetNumRecordElements
    >>mti_GetSignalSubelements
    >>and so on...
    >>
    >>the doc is on <yourlocalmodeltechinstall>/docs/se_html/se_fli/
    >>
    >>and also an example is
    >><modeltech>/examples/vhdl/foreign/example_four/foreignsp.vhd
    >>(this one is pure C)
    >>
    >>HTH and that we'll have a beer together one of these days!
    >>Stephane
    >>
    >>manu wrote:
    >>
    >>>Hi,
    >>>I'm using VHDL/SystemC cosimulation under Modelsim for validation of my
    >>>design.
    >>>All my synthesisable modules are written in VHDL and all my test benches
    >>>are written in SystemC since it offers very convenient features to build
    >>>complex test scenarios.
    >>>Until Now, it was OK since all my VHDL modules had "trivial" data types
    >>>on their ports (eg. std_logic and std_logic_vector). So the generation of
    >>>SystemC wrappers for my HDL modules was very easy thank to "scgenmod"
    >>>command.
    >>>Now, I want to use a custom data type like the following one :
    >>>
    >>>package mytypes is
    >>> type my_custom_type_t is record
    >>> my_flag : std_logic;
    >>> my_bus : std_logic_vector(WIDTH-1 downto 0);
    >>> more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    >>> ...
    >>> end record;
    >>>end package;
    >>>
    >>>and for my entity :
    >>>
    >>>entity mydesign_top is
    >>> port
    >>>(
    >>> custom_input : in my_custom_type_t;
    >>>
    >>> ...All my other stuff...
    >>>);
    >>>end mydesign_top;
    >>>
    >>>The problem is I don't know any "smart" way to bind a SytemC type to my
    >>>custom VHDL type. The only workaround I found for the moment is to
    >>>encapsulate my VHDL module into a VHDL wrapper in which I perform a
    >>>breakout of my custom type :
    >>>
    >>>entity mydesign_top_wrap is
    >>> port
    >>>(
    >>> --begin custom_input breakout
    >>> custom_input_flag : std_logic;
    >>> custom_input_bus : std_logic_vector(WIDTH-1 downto 0);
    >>> custom_input_more_stuff : std_logic_whatever(YOU_HAPPEN to NEED);
    >>> ...
    >>> --end custom_input breakout
    >>>
    >>> ...All my other stuff...
    >>>);
    >>>end mydesign_top_wrap;
    >>>
    >>>But I don't like this solution because it is very hard to maintain my
    >>>whole source code when I modify the definition of my_custom_type_t.
    >>>Idealy, I would like to have only two file to modify : the VHDL package
    >>>and a corresponding C++ header in which would be defined the type
    >>>mapping.
    >>>Does anyone know how to do this or any clean workaround ?
    >>>thanks for your help !
    >>>
    >>>Manu

    >
    >
    >
     
    manu, Apr 7, 2006
    #6
  7. manu

    ceg

    Joined:
    Mar 27, 2007
    Messages:
    3
    Is there anyone still left in this thread!.. i have a similar problem and i need help.. :-(
     
    ceg, Mar 27, 2007
    #7
  8. manu

    ceg

    Joined:
    Mar 27, 2007
    Messages:
    3
    guys.. i badly need help.. please reply asap
     
    ceg, Mar 29, 2007
    #8
  9. manu

    ceg

    Joined:
    Mar 27, 2007
    Messages:
    3
    actually my problem is i need to generate the SystemC wrapper for the VHDL code which has enumerated data types in it.. so how do i work around this problem or is there any way i can make scgenmod understand it!!!
     
    ceg, Mar 29, 2007
    #9
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