E
Edwin Naroska
Posted-By: auto-faq 3.3 (Perl 5.008)
This posting explains some ways to get the FAQ (Frequently Asked
Questions) of the newsgroup comp.lang.vhdl:
Besides of the monthly postings the FAQ is also available by
www at "http://www.vhdl.org/comp.lang.vhdl/" or
"http://www.eda.org/comp.lang.vhdl/" or
ftp on "vhdl.org /pub/comp.lang.vhdl/FAQ*" see VHDL
International for details on accessing the server
or send me a note to get a copy via e-mail. Further, all parts of the
FAQ are available in HTML format and PDF format (better suited for
printing).
The FAQ consists of *four* parts:
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (PD+commercial)
Part 4: VHDL Glossary
Part 4 is an ASCII representation of Annex B (Glossary) of the
IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual. This
glossary contains brief, informal descriptions for a number of terms
and phrases used to define VHDL. Additionally, it includes some
examples to illustrate various definitions.
The following link points to a HTML version of the glossary using
frames
http://www.vhdl.org/comp.lang.vhdl/html3/gloss_fr.html .
A version without frames is at
http://www.vhdl.org/comp.lang.vhdl/FAQ4.html .
For a chronological list of changes made to the FAQ see below.
Bye,...
Edwin
--------------------------------------------------------------------
Dr.-Ing. Edwin Naroska phone: ++49 231 7552406
Computer Engineering Institute fax: ++49 231 7553251
(Lehrstuhl fuer Datenverarbeitungssysteme)
University of Dortmund, 44221 Dortmund, Germany
--------------------------------------------------------------------
FAQ comp.lang.vhdl history (last 3 months)
Jun 2003
* Part 2, Section 2.8: recommendation counters updated
* Part 1, Section 4.2.40: text updated
* Part 1: links updated
* Part 1, Section : links to uP1232 (a 8-bit FPGA-based
microprocessor core;
http://www.dte.eis.uva.es/OpenProjects/OpenUP/index.htm),
DRAGONFLY microprocessor core
(http://www.leox.org/resources/dvlp.html#RES_DVLP_DGF), an 8-bit
Stack Processor
(http://www.compusmart.ab.ca/rc/Papers/8bitprocessor/stackproc.htm
l) and JOP (a Java Optimized Processor;
http://www.jopdesign.com/download.jsp) added
May 2003
* Part 2, Section 2: new book "Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for Assertion-Based
Verification" by Ben Cohen added to list
* Part 2, Section 2.4 and 3.2: the book VHDL, VHDL'87/'93 en
voorbeelden by Egbert Molenkamp can be downloaded for free from
http://wwwhome.cs.utwente.nl/~molenkam/DownloadVhdlBoek.htm
* Part 2, Section 3: A PSL VHDL Quick reference card is available
from
http://members.aol.com/vhdlcohen/vhdl/vhdlcode/PSL_quickrefvhdl.pd
f
* Part 1, Section 4.10: MicroCore, a simple micro controller core
targeting FPGAs is available from
http://www.microcore.org/index.html
* Part 1, Section 4.10: the Confluence LDPC Decoder can be
downloaded from http://www.opencores.org/projects/cf_ldpc/
* Part 1, Section 4.2.12: section extended
Apr 2003
* Part 1, Section 3.1: an online VHDL language guide by Altium
Limited is at http://www.acc-eda.com/vhdlref/index.html
* Part 2, Section 3.1: the document entitled "An Introduction to
HDLs for Simulation and Synthesis" by David Pellerin is available
from http://www.acc-eda.com/support/vhdpaper.pdf
* Part 3, Section 3.2: entry for Simulator PeakVHDL (the simulator
is now part of nVisage DXP) and DirectVHDL (now also supports Mac
OS X)
* Part 1: links updated
* Part 3, Section 1.5: entry for HDLmaker updated
* Part 2, Section 3: link to the Amontec VHDL Memo added
(http://www.amontec.com/fix/vhdl_memo/index.html)
* Part 2, Section 2 and 3.2: The VHDL Cookbook by Peter J. Ashenden
is also available from
http://www3.cti.ac.at/ecsi/EARNEST/digests/VHDL_cookbook/default.h
tm
* Part 1, Section 4.10: A minimal 8 bit VHDL CPU designed for a 32
macrocell CPLD is available from
(http://www.tu-harburg.de/~setb0209/cpu/mcpu.html)
* Part 3, Section 4.1: link to Verilog to free VHDL RTL converter by
John Sheahan added (http://www.reptechnic.com.au/v2vhd.html)
* Part 1, Section 4.10: link to package containing various function
to convert between hex/decimal/octal/binary strings and
std_logic(_vector)/natural added
(http://www.eda.org/fmf/fmf_public_models/packages/conversions.vhd
)
This posting explains some ways to get the FAQ (Frequently Asked
Questions) of the newsgroup comp.lang.vhdl:
Besides of the monthly postings the FAQ is also available by
www at "http://www.vhdl.org/comp.lang.vhdl/" or
"http://www.eda.org/comp.lang.vhdl/" or
ftp on "vhdl.org /pub/comp.lang.vhdl/FAQ*" see VHDL
International for details on accessing the server
or send me a note to get a copy via e-mail. Further, all parts of the
FAQ are available in HTML format and PDF format (better suited for
printing).
The FAQ consists of *four* parts:
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (PD+commercial)
Part 4: VHDL Glossary
Part 4 is an ASCII representation of Annex B (Glossary) of the
IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual. This
glossary contains brief, informal descriptions for a number of terms
and phrases used to define VHDL. Additionally, it includes some
examples to illustrate various definitions.
The following link points to a HTML version of the glossary using
frames
http://www.vhdl.org/comp.lang.vhdl/html3/gloss_fr.html .
A version without frames is at
http://www.vhdl.org/comp.lang.vhdl/FAQ4.html .
For a chronological list of changes made to the FAQ see below.
Bye,...
Edwin
--------------------------------------------------------------------
Dr.-Ing. Edwin Naroska phone: ++49 231 7552406
Computer Engineering Institute fax: ++49 231 7553251
(Lehrstuhl fuer Datenverarbeitungssysteme)
University of Dortmund, 44221 Dortmund, Germany
--------------------------------------------------------------------
FAQ comp.lang.vhdl history (last 3 months)
Jun 2003
* Part 2, Section 2.8: recommendation counters updated
* Part 1, Section 4.2.40: text updated
* Part 1: links updated
* Part 1, Section : links to uP1232 (a 8-bit FPGA-based
microprocessor core;
http://www.dte.eis.uva.es/OpenProjects/OpenUP/index.htm),
DRAGONFLY microprocessor core
(http://www.leox.org/resources/dvlp.html#RES_DVLP_DGF), an 8-bit
Stack Processor
(http://www.compusmart.ab.ca/rc/Papers/8bitprocessor/stackproc.htm
l) and JOP (a Java Optimized Processor;
http://www.jopdesign.com/download.jsp) added
May 2003
* Part 2, Section 2: new book "Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for Assertion-Based
Verification" by Ben Cohen added to list
* Part 2, Section 2.4 and 3.2: the book VHDL, VHDL'87/'93 en
voorbeelden by Egbert Molenkamp can be downloaded for free from
http://wwwhome.cs.utwente.nl/~molenkam/DownloadVhdlBoek.htm
* Part 2, Section 3: A PSL VHDL Quick reference card is available
from
http://members.aol.com/vhdlcohen/vhdl/vhdlcode/PSL_quickrefvhdl.pd
f
* Part 1, Section 4.10: MicroCore, a simple micro controller core
targeting FPGAs is available from
http://www.microcore.org/index.html
* Part 1, Section 4.10: the Confluence LDPC Decoder can be
downloaded from http://www.opencores.org/projects/cf_ldpc/
* Part 1, Section 4.2.12: section extended
Apr 2003
* Part 1, Section 3.1: an online VHDL language guide by Altium
Limited is at http://www.acc-eda.com/vhdlref/index.html
* Part 2, Section 3.1: the document entitled "An Introduction to
HDLs for Simulation and Synthesis" by David Pellerin is available
from http://www.acc-eda.com/support/vhdpaper.pdf
* Part 3, Section 3.2: entry for Simulator PeakVHDL (the simulator
is now part of nVisage DXP) and DirectVHDL (now also supports Mac
OS X)
* Part 1: links updated
* Part 3, Section 1.5: entry for HDLmaker updated
* Part 2, Section 3: link to the Amontec VHDL Memo added
(http://www.amontec.com/fix/vhdl_memo/index.html)
* Part 2, Section 2 and 3.2: The VHDL Cookbook by Peter J. Ashenden
is also available from
http://www3.cti.ac.at/ecsi/EARNEST/digests/VHDL_cookbook/default.h
tm
* Part 1, Section 4.10: A minimal 8 bit VHDL CPU designed for a 32
macrocell CPLD is available from
(http://www.tu-harburg.de/~setb0209/cpu/mcpu.html)
* Part 3, Section 4.1: link to Verilog to free VHDL RTL converter by
John Sheahan added (http://www.reptechnic.com.au/v2vhd.html)
* Part 1, Section 4.10: link to package containing various function
to convert between hex/decimal/octal/binary strings and
std_logic(_vector)/natural added
(http://www.eda.org/fmf/fmf_public_models/packages/conversions.vhd
)
