what are the possible reasons that successful pre-synthesis simulation + successful synthesis = fail

[walala]

Dear all,

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
internal nodes have "1", and the other internal nodes have "X"... but the
internal nodes were stuck with their values: the "0"s were always "0", the
"1"s were always "1", the "X"s were always "X"...

Worth noting is that I follow the same workflow for some very small designs,
it worked perfectly... but now it failed for medium-big size design...

I feel the errors are so systemetic, which may be caused by some hidden
tricks(for large size design) in Synopsys DC that I did not know...

Can anybody help me out of this swamp?

Thanks:

--------------------------------------------------------------
My script file:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct.log {
analyze -format vhdl -lib WORK {myidct.vhd}
elaborate myidct -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "clk" -name "clk" -period 10
compile -map_effort medium
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
reports/\$current_d
esign.rep
report_area >> reports/\$current_design.rep
change_names -rules vhdl
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
plot -hierarchy -output "schematic/\$current_design.ps"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

---------------------------------------------------------

 

[Ralf Hildebrandt]

Hi walala!

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", ...

Split your design into smaller components. Run synthesis step-by-step,
only one new synthesized components at a time.

Think about hazards (glitches). Do have latches within your design? - If
yes, think carefully about run-time - problems.

And last of all: Don't "program" a chip with VHDL - chips have to be
designed / described. Think about every line of code, what it could be
synthesized to.

Ralf

 

[walala]

Hi Ralf,

Thank you very much for your answer!

Split your design into smaller components. Run synthesis step-by-step,
only one new synthesized components at a time.

Good idea! I will try out!

Think about hazards (glitches). Do have latches within your design? - If
yes, think carefully about run-time - problems.

And last of all: Don't "program" a chip with VHDL - chips have to be
designed / described. Think about every line of code, what it could be
synthesized to.

That's my problem. I really have no idea what each line of code will be
synthesized to;

sometimes relocating some sentences will change the whole hardware.

I guess the code was synthesized to the hardware I did not expect...(see my
another post -- newbie question about synthesizable VHDL code)

Are there any books/online resources can help me familiar with which code
synthesize to what hardware? or this is just a purely experience based
learning process that only the old veteran will know the tricks?

Ralf

-Walala

 

[Renaud Pacalet]

Dear all,

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
internal nodes have "1", and the other internal nodes have "X"... but the
internal nodes were stuck with their values: the "0"s were always "0", the
"1"s were always "1", the "X"s were always "X"...

Worth noting is that I follow the same workflow for some very small designs,
it worked perfectly... but now it failed for medium-big size design...

I feel the errors are so systemetic, which may be caused by some hidden
tricks(for large size design) in Synopsys DC that I did not know...

Can anybody help me out of this swamp?

A problem of pre-post synthesis simulations mismatches is usually not a
synthesis script problem. It usually comes from a pre-synthesis model
describing something that cannot be implemented on the target
technology. Most synthesizers raise warnings when they encounter
unsupported or partially supported statements. Did you carefully read dc
warnings. If yes post your pre-synthesis VHDL and we'll tell you what's
wrong.

Regards,

 

[Ralf Hildebrandt]

Hi walala!

That's my problem. I really have no idea what each line of code will be
synthesized to;

A very small list:
http://groups.google.de/[email protected]&rnum=1

Are there any books/online resources can help me familiar with which code
synthesize to what hardware? or this is just a purely experience based
learning process that only the old veteran will know the tricks?

Every HDL book should tell you this stuff. The problem is, that most
books will not recommend a single template for every problem, because
nobody is perferct and it is the skill of the designer to build _new_
efficient descriptions.


Ralf