What is meant by Static name

Discussion in 'VHDL' started by Mohammed A khader, Mar 1, 2005.

  1. Hi all,

    when I was compiling this function I got the error saying..
    aliased object name must be a static name.

    function STR(Data_In : in std_logic_vector ) return string is
    alias data : std_logic_vector(1 to Data_In'LENGTH) is
    Data_In(Data_In'LENGTH-1 DOWNTO 0);
    variable result : string(1 to Data_In'LENGTH);
    begin
    for i in 1 to Data_In'LENGTH loop

    result(i) := Std_Table(Data(i));


    end loop;
    return result;
    end function STR;

    But it worked with this...
    alias data : std_logic_vector(1 to Data_In'LENGTH) is Data_In;

    I would like to know what is actually meant by 'static' name.
    Thanks in Advance.

    Mohammed Khader.
     
    Mohammed A khader, Mar 1, 2005
    #1
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  2. Mohammed A khader wrote:

    > when I was compiling this function I got the error saying..
    > aliased object name must be a static name.


    > But it worked with this...
    > alias data : std_logic_vector(1 to Data_In'LENGTH) is Data_In;
    > I would like to know what is actually meant by 'static' name.


    A slice of a static object is not static.
    Maybe you can do the slice using a local
    function/procedure variable.

    -- Mike Treseler
     
    Mike Treseler, Mar 1, 2005
    #2
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  3. But if slice index (indcies defining the slice of the object) is
    also static then it should be considered as a static .
     
    Mohammed A khader, Mar 2, 2005
    #3
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