What is the base type?

Discussion in 'VHDL' started by Valentin Tihhomirov, Jan 20, 2013.

  1. Is it the immediate predecessor of the subtype or it is the root,
    declared by type_definition or predefined superroot (e.g.
    $universal_integer)?

    From the

    qualified_expression ::= type_mark ' ( expression )

    and statement *"The operand shall have the same type as the base typeof
    the type mark"* it follows that the base type is the root because
    literals are of the root type rather than immediate predcessor.

    On the other hand, the "Subtypes" section in Ashenden creates an
    impression that the base base type is not the root but immediate
    predecessor: "We can represent such objects by declaring a subtype,
    which defines a restricted set of values from a base type.. The sub-type
    declaration defines the identifier as a subtype of the base type
    specified by the type mark" And, I see in the "Type Declarations"
    section, which remarks that two declared types with are different
    despite the same definition, does not mention that declarations define
    the base types.


    LRM Section on types does not clarify the things:

    "A subtypeis a type together with a constraint. A value is said to
    belong to a subtypeof a given type if it belongs to the type and
    satisfies the constraint; the given type is called the base typeof the
    subtype. A type is a subtype of itself; such a subtype is said to be
    unconstrained (it corresponds to a condition that imposes no
    restriction). The base type of a type is the type itself."


    Apart from that, what is the point of defining both type and subtype,
    ("array_definition defines both an array type and a subtype of this type")?
    Valentin Tihhomirov, Jan 20, 2013
    #1
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  2. Valentin Tihhomirov

    valtih1978 Guest

    > LRM Section on types does not clarify the things:
    "A subtypeis a type together with a constraint. A value is said to
    belong to a subtypeof a given type if it belongs to the type and
    satisfies the constraint; the given type is called the base typeof the
    subtype. A type is a subtype of itself; such a subtype is said to be
    unconstrained (it corresponds to a condition that imposes no
    restriction). The base type of a type is the type itself."

    Could you please clarify? Does it say that subtypes are always based on
    the root type rather than form a hierarchy of subtypes?
    valtih1978, Jan 22, 2013
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  3. Valentin Tihhomirov

    valtih1978 Guest

    subtype ST is INTEGER range 1 to 10;
    subtype SST is INTEGER range 2 to 8;

    report SST'base'low

    will print "-2147483648". That is, it seems that there is no hierarchy
    of subtypes in VHDL. A subtype-based subtype is grandtype based behind
    the scenes.
    valtih1978, Jan 26, 2013
    #3
  4. Valentin Tihhomirov

    valtih1978 Guest

    summarizing

    Summarizing Alan Fitch notes:

    subtype TSHORT is INTEGER range 1 to 2;
    subtype TSMALL is INTEGER range 4 to 6;
    variable short: TSHORT;
    variable small: TSMALL;

    small := short; // failed during execution

    This is acceptable and elaboration will not complain because subtypes
    are compatible. They belong to the same type, the base. The type system
    is flat again (if we do not consider the universal and other
    supertypes). No matter if subtypes were declared over another subtype.
    The base type is extracted from the subtype used as base and will be
    used for defining a new subtype. For example, INTEGER will be the base
    type for VERY_SMALL declared as

    subtype VERY_SMALL is TSMALL range (4 to 6)
    valtih1978, Jan 26, 2013
    #4
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