While compiling

[Be myself]

Once I take one VHDL code into ModelSim,
make the tool compiling code,I found some syntax error message.
Thus this action failed.

While,the same code can pass the verification of max-plus2 .
.....
I can't figure out this result. ???

 

[Brent Hayhoe]

Once I take one VHDL code into ModelSim,
make the tool compiling code,I found some syntax error message.
Thus this action failed.

While,the same code can pass the verification of max-plus2 .
....
I can't figure out this result. ???

Neither can anyone else without some more information than this!

--

Regards,

Brent Hayhoe.

Aftonroy Limited
Email: <A
HREF="mailto:[email protected]">

 

[Tero Kapanen]

Neither can anyone else without some more information than this!

I want to try anyway.

Check that you have VHDL-93 enabled.

Right-click the vhdl-file, Properties and under VHDL tab there is "use 1993
Language Syntax".

- tero