While compiling

Discussion in 'VHDL' started by Be myself, Nov 11, 2003.

  1. Be myself

    Be myself Guest

    Once I take one VHDL code into ModelSim,
    make the tool compiling code,I found some syntax error message.
    Thus this action failed.

    While,the same code can pass the verification of max-plus2 .
    .....
    I can't figure out this result. ???
    --
     ¡°µo«H¯¸: º~¯«¤p¯¸ <bbs.ee.nsysu.edu.tw>
     ¡» From: pailiou.ee.nsysu.edu.tw
    Be myself, Nov 11, 2003
    #1
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  2. Be myself

    Brent Hayhoe Guest

    Be myself wrote:
    > Once I take one VHDL code into ModelSim,
    > make the tool compiling code,I found some syntax error message.
    > Thus this action failed.
    >
    > While,the same code can pass the verification of max-plus2 .
    > ....
    > I can't figure out this result. ???


    Neither can anyone else without some more information than this!

    > --
    >  ¡°µo«H¯¸: º~¯«¤p¯¸ <bbs.ee.nsysu.edu.tw>
    >  ¡» From: pailiou.ee.nsysu.edu.tw


    --

    Regards,

    Brent Hayhoe.

    Aftonroy Limited
    Email: <A
    HREF="mailto:">
    Brent Hayhoe, Nov 11, 2003
    #2
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  3. Be myself

    Tero Kapanen Guest

    "Brent Hayhoe" <> wrote in message
    news:boq2ll$nbp$...
    > > I can't figure out this result. ???

    >
    > Neither can anyone else without some more information than this!
    >


    I want to try anyway. :)

    Check that you have VHDL-93 enabled.

    Right-click the vhdl-file, Properties and under VHDL tab there is "use 1993
    Language Syntax".

    - tero
    Tero Kapanen, Nov 11, 2003
    #3
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