Why on Simulation the result is not what is expected?

Discussion in 'VHDL' started by b.g.dariush@gmail.com, Nov 18, 2012.

  1. Guest

    Hey guys
    I have a presentation for next couple days on VHDL and i need to show
    some simple example project, I managed to write a <b>4 Bit Adder</b> as
    follow:
    Adder4.vhd:
    --------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    ENTITY Adder4 IS
    PORT
    (
    Cin : IN STD_LOGIC;
    X, Y : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
    R : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
    Cout : OUT STD_LOGIC
    );
    END Adder4;

    ARCHITECTURE Adder4_Behav OF Adder4 IS
    SIGNAL Carry : STD_LOGIC_VECTOR ( 2 DOWNTO 0);

    COMPONENT FullAdder
    PORT
    (
    Cin, A, B : IN STD_LOGIC;
    Cout, S : OUT STD_LOGIC
    );
    END COMPONENT;
    BEGIN
    FA0: FullAdder PORT MAP ( Cin, X(0), Y(0), Carry(0), R(0));
    FA1: FullAdder PORT MAP ( Carry(0), X(1), Y(1), Carry(1), R(1));
    FA3: FullAdder PORT MAP ( Carry(1),X(2),Y(2),Carry(2),R(2));
    FA4: FullAdder PORT MAP ( Carry(2),X(3),Y(3),Cout,R(3));
    END;
    --------------------------------------------------------------------------------

    FullAdder.vhd

    --------------------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    ENTITY FullAdder IS
    PORT
    (
    Cin, A, B : IN STD_LOGIC;
    Cout, S : OUT STD_LOGIC
    );
    END FullAdder;

    ARCHITECTURE FullAdder_Behav OF FullAdder IS
    BEGIN
    S <= A XOR B XOR Cin;
    Cout <= (A AND Cin) OR (B AND Cin) OR (A AND B);
    END;
    --------------------------------------------------------------------------------

    but when i run simulation the output result is not synced at all!
    I know i am not considering something here, but what is that?
    I need HELP ASAP, please :(
    What is it that i am doing wrong!?

    I don't see any attachment option here
    but i have uploaded the .vwf and the simulation result as attachments
    in
    http://embdev.net/attachment/160752/Vector_Wave_File.png

    AND

    http://embdev.net/attachment/160753/Simu_Result.jpg

    Thanks in advace
    , Nov 18, 2012
    #1
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  2. Le 18/11/2012 20:36, a écrit :
    > Hey guys

    [...]
    > but when i run simulation the output result is not synced at all!
    > I know i am not considering something here, but what is that?
    > I need HELP ASAP, please :(
    > What is it that i am doing wrong!?


    Absolutely nothing.
    You are simulating an implemented design and what you see is actual gate
    delays. That's how the real world works. What did you expect ?

    Nicolas
    Nicolas Matringe, Nov 18, 2012
    #2
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  3. rickman Guest

    On 11/18/2012 2:36 PM, wrote:
    > Hey guys
    > I have a presentation for next couple days on VHDL and i need to show
    > some simple example project, I managed to write a<b>4 Bit Adder</b> as
    > follow:
    > Adder4.vhd:
    > --------------------------------------------------------------------------------
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > ENTITY Adder4 IS
    > PORT
    > (
    > Cin : IN STD_LOGIC;
    > X, Y : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
    > R : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
    > Cout : OUT STD_LOGIC
    > );
    > END Adder4;
    >
    > ARCHITECTURE Adder4_Behav OF Adder4 IS
    > SIGNAL Carry : STD_LOGIC_VECTOR ( 2 DOWNTO 0);
    >
    > COMPONENT FullAdder
    > PORT
    > (
    > Cin, A, B : IN STD_LOGIC;
    > Cout, S : OUT STD_LOGIC
    > );
    > END COMPONENT;
    > BEGIN
    > FA0: FullAdder PORT MAP ( Cin, X(0), Y(0), Carry(0), R(0));
    > FA1: FullAdder PORT MAP ( Carry(0), X(1), Y(1), Carry(1), R(1));
    > FA3: FullAdder PORT MAP ( Carry(1),X(2),Y(2),Carry(2),R(2));
    > FA4: FullAdder PORT MAP ( Carry(2),X(3),Y(3),Cout,R(3));
    > END;
    > --------------------------------------------------------------------------------
    >
    > FullAdder.vhd
    >
    > --------------------------------------------------------------------------------
    > library ieee;
    > use ieee.std_logic_1164.all;
    >
    > ENTITY FullAdder IS
    > PORT
    > (
    > Cin, A, B : IN STD_LOGIC;
    > Cout, S : OUT STD_LOGIC
    > );
    > END FullAdder;
    >
    > ARCHITECTURE FullAdder_Behav OF FullAdder IS
    > BEGIN
    > S<= A XOR B XOR Cin;
    > Cout<= (A AND Cin) OR (B AND Cin) OR (A AND B);
    > END;
    > --------------------------------------------------------------------------------
    >
    > but when i run simulation the output result is not synced at all!
    > I know i am not considering something here, but what is that?
    > I need HELP ASAP, please :(
    > What is it that i am doing wrong!?
    >
    > I don't see any attachment option here
    > but i have uploaded the .vwf and the simulation result as attachments
    > in
    > http://embdev.net/attachment/160752/Vector_Wave_File.png
    >
    > AND
    >
    > http://embdev.net/attachment/160753/Simu_Result.jpg
    >
    > Thanks in advace


    You didn't show the test bench file you are using. My guess is that in
    your test bench you are generating the X, Y and Cin signals, then
    running them through registers before they reach the full adder. It
    looks like you are using a 10 nS (100 MHz) clock.

    The changes that occur just after the inputs change at 20 and 30 ns in
    the latter image are the result of logic delay times. You seem to be
    running a timing mode simulation. These will go away if you run a logic
    mode simulation which is just on the VHDL code and not on the placed and
    routed chip.

    Can we see your test bench file? Oh, I see the first image is a vector
    file. Is that your stimulus? I don't think I have done that in a long,
    long time. You might try writing a test bench instead.

    Rick
    rickman, Nov 18, 2012
    #3
  4. Guest

    Am Sonntag, 18. November 2012 22:46:16 UTC+1 schrieb Nicolas Matringe:
    > Le 18/11/2012 20:36, b.g. a écrit :
    >
    > > Hey guys

    >
    > [...]
    >
    > > but when i run simulation the output result is not synced at all!

    >
    > > I know i am not considering something here, but what is that?

    >
    > > I need HELP ASAP, please :(

    >
    > > What is it that i am doing wrong!?

    >
    >
    >
    > Absolutely nothing.
    >
    > You are simulating an implemented design and what you see is actual gate
    >
    > delays. That's how the real world works. What did you expect ?
    >
    >
    >
    > Nicolas


    Hi,
    I'm not sure about the behavior of the Quartus simulation tool,
    But even if this simple combinatorical circuit has been simulated in timingsim mode, why is the first result there immediately (t=0).
    Also the inputs seem to be applied to the actual circuit quite late (exceptfor t=0). This might irritate a beginner, because one would expect something different from a simple combinatorical circuit. It might be something caused by this vector file simulation.

    As rickman suggested, a HDL Tesbench would be useful.

    Have a nice simulation
    Eilert
    , Nov 19, 2012
    #4
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