Xilinx Core Asynchronous FIFO Limits not being set

[maurizio]

Has anyone been having problems with Asynchronous FIFO cores generated
by fifo core gen 2.3 ?

My cores ignores the thresholds at which the fifo becomes full or empty
when I set them either as a constant through the core gen or externally
through prog_empty_thresh or prog_full_thresh ?

Any ideas ?

M.Gencarelli
Defence Science&Technology Organisation
Australia

 

[Newman]

Has anyone been having problems with Asynchronous FIFO cores generated
by fifo core gen 2.3 ?

My cores ignores the thresholds at which the fifo becomes full or empty
when I set them either as a constant through the core gen or externally
through prog_empty_thresh or prog_full_thresh ?

Any ideas ?

M.Gencarelli
Defence Science&Technology Organisation
Australia

The comp.arch.fpga group is probably a better place to post this
question.
You may want to read Xilinx fifo_generator_ds317.pdf
You mentioned the flags FULL and EMPTY. Did you mean PROG_FULL and
PROG_EMPTY?
I believe that these are the flags controlled by the thresholds you
mentioned.

Hope this helps.
Newman