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Can anyone think of a workaround - Ideally I want to pass an accesstype into an entity (not for synt
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[QUOTE="Tricky, post: 4200967"] Im building a model of a memory interface. The entity mimics the interface of the normal memory interface with multiple request, address, ack and data valid lines, one set per channel. Internally I have a protected type that handles the memory modelling (dynamically creating memory locations as they are accessed so I dont have a monstrous 256Mbyte array declared) and another protected that handles the read queue. As this is modelling a memory in a video system, I want to be able to dump whole images (ie bypassing the whole interface) into memory, for example if Im only testing the other bits of the design on the read side of the interface. I have everything I need for reading/writing bitmaps to specific array types, but I just need to get these arrays into this entity. Heres the pinch - I really dont want to specify the size of the image, as this may well handle multiple video standards on hardware, so I need the image sizes to vary accordingly. Id love to be able to pass in an access type and watch the transactions on it - but of course access types can only be variables - therefore not suitable for ports on an entity. Can anyone think of any other way I could get these arrays into the interface without padding? The only thing I can think of is sticking image sizes as generics and declaring the "image" port to this size, but I would prefer more flexibility. So - am I just pushing too hard? How long before someone pipes up that I should try System Verilog? [/QUOTE]
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Can anyone think of a workaround - Ideally I want to pass an accesstype into an entity (not for synt
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