VHDL

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comp.lang.vhdl
B
Clock divide by 5
  • blesssy
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0
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72
blesssy
B
Q
How to check time delay caused by code itself?
  • Quuruu
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1
Views
71
Quuruu
Q
H
Some Cash for Vhdl coding
  • Harry12
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0
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113
Harry12
H
H
Vhdl coding
  • Harry12
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0
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96
Harry12
H
R
Can anyone please help me in this code
  • ragerrani
Replies
1
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163
TheAliceMay
T
A
What is `transaction`event
  • Ash72
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0
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98
Ash72
A
R
Low level block coding
  • Roger31415
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0
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103
Roger31415
R
C
VHDL code for multiplier
  • chi_rulez
Replies
8
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23K
Hao
H
A
What does 'genbin' and 'addbins' in OSVVM mean?
  • Ash72
Replies
0
Views
138
Ash72
A
D
Binary to BCD code understanding
  • div_01
Replies
0
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314
div_01
D
N
Outputting signal values to terminal Within Character Array
  • new_guy_505
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0
Views
320
new_guy_505
N
L
Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
Replies
0
Views
562
Luis7910
L
L
Lattice EFB I2C core works in simulation, but not on hardware
  • littlegamer
Replies
3
Views
5K
lars555
L
P
character to std_logic_vector
  • Pedro Claro
Replies
8
Views
33K
furqhan
F
M
Convert boolean to std_logic
  • manolis kaliorakis
Replies
3
Views
26K
cube1us
C
N
VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
Replies
0
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2K
Nikos_for_vhdl
N
A
Modelsim simulation Problem?
  • alexglvr
Replies
3
Views
2K
GopikaCB
G
M
VHDL multiplier
  • mk7899
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0
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1K
mk7899
M
K
Register clear on read
  • kamalre
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0
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2K
kamalre
K
X
IC 74374-getting incorrect simulation
  • xorro
Replies
0
Views
878
xorro
X
D
2 JK Circuit in VHDL
  • dumdumdum
Replies
0
Views
847
dumdumdum
D
T
conv_std_logic_vector
  • trescot
Replies
5
Views
27K
bala6007
B
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
Replies
0
Views
883
ADHUL
A
V
Sum of element array
  • VHDL_HELP
Replies
2
Views
1K
alireza95
A
A
sum of a array's element
  • alireza95
Replies
0
Views
817
alireza95
A
A
reading binary file using vhdl
  • assaad EL Makhloufi
Replies
0
Views
783
assaad EL Makhloufi
A
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
Replies
0
Views
928
JaneJune
J
A
Problem With Mealy Sequence Detector
  • Armand
Replies
1
Views
829
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
Replies
0
Views
927
Cor
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
Replies
1
Views
3K
Cor
C
L
LFSR doesn't generate random values during simulation
  • learni
Replies
1
Views
1K
Cor
C
L
Cannot Read Data in 1-Port RAM IP Core
  • learni
Replies
0
Views
898
learni
L
A
How to write if statement written in matlab with vhdl ?
  • afef
Replies
0
Views
757
afef
A
A
Converting VHDL to XML
  • avishay
Replies
4
Views
4K
Fahad Majeed
Fahad Majeed
A
verilog, rtl, simulation
Replies
0
Views
947
[email protected]
A
S
Reading an xml file in vhdl
  • sandeepthi
Replies
0
Views
1K
sandeepthi
S
A
need to count constants names in vhdl
  • Ana
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0
Views
2K
Ana
A
R
Verilog code for MD5 algorithm
  • raag2c
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2
Views
4K
akshata.j
A
K
Comparing Inputs to Outputs Simon Game
  • KC1
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0
Views
1K
KC1
K
K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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0
Views
946
Kritika Bhardwaj
K
S
verilog hdl
  • shachi
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0
Views
960
shachi
S
C
Illegal sequential statement (VHDL)
  • chiraz
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0
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2K
chiraz
C
A
lms algorithm code
  • alok das gupta
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0
Views
1K
alok das gupta
A
L
Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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0
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1K
Larinayo
L
A
VHDL Subtraction two’s complement
  • Alenx
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0
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2K
Alenx
A
A
2 flip-flop synchronizer
  • andys86498
Replies
1
Views
2K
netguy63
N
Z
Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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0
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1K
Zo Ki
Z
A
ASIC RTL and FPGA RTL
  • Anand P Paralkar
Replies
2
Views
9K
Yasir Khizar
Y
A
How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
Replies
0
Views
2K
Anwesa Roy
A
R
Input ports in VHDL of type string and Boolean
  • Razn_957
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0
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2K
Razn_957
R
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