VHDL

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comp.lang.vhdl
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Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
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0
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302
Luis7910
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Lattice EFB I2C core works in simulation, but not on hardware
  • littlegamer
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3
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4K
lars555
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character to std_logic_vector
  • Pedro Claro
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8
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32K
furqhan
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Convert boolean to std_logic
  • manolis kaliorakis
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3
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23K
cube1us
C
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VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
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0
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2K
Nikos_for_vhdl
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Modelsim simulation Problem?
  • alexglvr
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3
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2K
GopikaCB
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VHDL multiplier
  • mk7899
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0
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949
mk7899
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Register clear on read
  • kamalre
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0
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2K
kamalre
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IC 74374-getting incorrect simulation
  • xorro
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0
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733
xorro
X
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2 JK Circuit in VHDL
  • dumdumdum
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0
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724
dumdumdum
D
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conv_std_logic_vector
  • trescot
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5
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27K
bala6007
B
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
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0
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770
ADHUL
A
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Sum of element array
  • VHDL_HELP
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2
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1K
alireza95
A
A
sum of a array's element
  • alireza95
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0
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697
alireza95
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reading binary file using vhdl
  • assaad EL Makhloufi
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0
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699
assaad EL Makhloufi
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Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
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0
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802
JaneJune
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Problem With Mealy Sequence Detector
  • Armand
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1
Views
724
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
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0
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690
Cor
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
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1
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2K
Cor
C
L
LFSR doesn't generate random values during simulation
  • learni
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1
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845
Cor
C
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Cannot Read Data in 1-Port RAM IP Core
  • learni
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0
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806
learni
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How to write if statement written in matlab with vhdl ?
  • afef
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0
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667
afef
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A
Converting VHDL to XML
  • avishay
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4
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4K
Fahad Majeed
Fahad Majeed
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verilog, rtl, simulation
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0
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851
[email protected]
A
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Reading an xml file in vhdl
  • sandeepthi
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0
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1K
sandeepthi
S
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need to count constants names in vhdl
  • Ana
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0
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1K
Ana
A
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Verilog code for MD5 algorithm
  • raag2c
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2
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4K
akshata.j
A
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Comparing Inputs to Outputs Simon Game
  • KC1
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0
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938
KC1
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K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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0
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822
Kritika Bhardwaj
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verilog hdl
  • shachi
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0
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883
shachi
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Illegal sequential statement (VHDL)
  • chiraz
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0
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1K
chiraz
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lms algorithm code
  • alok das gupta
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0
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1K
alok das gupta
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Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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0
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1K
Larinayo
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VHDL Subtraction two’s complement
  • Alenx
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0
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2K
Alenx
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A
2 flip-flop synchronizer
  • andys86498
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1
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2K
netguy63
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Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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0
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975
Zo Ki
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A
ASIC RTL and FPGA RTL
  • Anand P Paralkar
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2
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8K
Yasir Khizar
Y
A
How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
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0
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1K
Anwesa Roy
A
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Input ports in VHDL of type string and Boolean
  • Razn_957
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0
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2K
Razn_957
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R
Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
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1
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1K
Rashnak
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miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
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0
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1K
miroslavasadov
miroslavasadov
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I need a VHDL code
  • Moh
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0
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1K
Moh
M
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and operator overloading
  • eladsolomon
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0
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1K
eladsolomon
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1:8 demux behavioral and structural modeling
  • Ibra1950
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1
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7K
Ibra1950
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Floating point library RC
  • Gonzalo
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0
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1K
Gonzalo
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VHDL 2005, VHDL93 and FPHDL
  • vijay
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3
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2K
Gonzalo
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Minimum period: No path found
  • kiran77
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0
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2K
kiran77
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Shift left register using VHDL shift operator : sll trouble
  • Anviori
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0
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1K
Anviori
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4 bit two flipflop sychronizer
  • Bhakti Dedhia
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0
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1K
Bhakti Dedhia
B
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FPGA for Frequency Divider
  • _Jaiko007
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0
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1K
_Jaiko007
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