VHDL

comp.lang.vhdl

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  1. Nikos_for_vhdl

    VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset

    Nikos_for_vhdl, Aug 27, 2020
    Replies:
    0
    Views:
    1,144
    Nikos_for_vhdl
    Aug 27, 2020
  2. alexglvr

    Modelsim simulation Problem?

    alexglvr, Jun 16, 2009
    Replies:
    3
    Views:
    2,059
    GopikaCB
    Aug 25, 2020
  3. mk7899

    VHDL multiplier

    mk7899, Jul 4, 2019
    Replies:
    0
    Views:
    712
    mk7899
    Jul 4, 2019
  4. kamalre

    Register clear on read

    kamalre, Jun 7, 2019
    Replies:
    0
    Views:
    1,415
    kamalre
    Jun 7, 2019
  5. xorro

    IC 74374-getting incorrect simulation

    xorro, Apr 26, 2019
    Replies:
    0
    Views:
    571
    xorro
    Apr 26, 2019
  6. dumdumdum

    2 JK Circuit in VHDL

    dumdumdum, Mar 29, 2019
    Replies:
    0
    Views:
    545
    dumdumdum
    Mar 29, 2019
  7. trescot

    conv_std_logic_vector

    trescot, Dec 12, 2006
    Replies:
    5
    Views:
    26,526
    bala6007
    Dec 27, 2018
  8. ADHUL

    Cannot find <math_utility_pkg> in library <ieee_proposed>

    ADHUL, Oct 13, 2018
    Replies:
    0
    Views:
    581
    ADHUL
    Oct 13, 2018
  9. VHDL_HELP

    Sum of element array

    VHDL_HELP, Mar 13, 2007
    Replies:
    2
    Views:
    1,235
    alireza95
    Jun 28, 2018
  10. alireza95

    sum of a array's element

    alireza95, Jun 28, 2018
    Replies:
    0
    Views:
    563
    alireza95
    Jun 28, 2018
  11. assaad EL Makhloufi

    reading binary file using vhdl

    assaad EL Makhloufi, Feb 26, 2018
    Replies:
    0
    Views:
    563
    assaad EL Makhloufi
    Feb 26, 2018
  12. JaneJune

    Sine wave 200khz , having a digital 16 bit value using VHDL

    JaneJune, Oct 23, 2017
    Replies:
    0
    Views:
    659
    JaneJune
    Oct 23, 2017
  13. Armand

    Problem With Mealy Sequence Detector

    Armand, Sep 1, 2017
    Replies:
    1
    Views:
    605
    Cor
    Oct 13, 2017
  14. Cor

    How to get signal name as a string in a procedure?

    Cor, Oct 13, 2017
    Replies:
    0
    Views:
    543
    Cor
    Oct 13, 2017
  15. alok das gupta

    conversion from 8bit to 4 bit in vhdl

    alok das gupta, Jan 10, 2017
    Replies:
    1
    Views:
    1,813
    Cor
    Oct 13, 2017
  16. learni

    LFSR doesn't generate random values during simulation

    learni, Aug 4, 2017
    Replies:
    1
    Views:
    648
    Cor
    Oct 13, 2017
  17. learni

    Cannot Read Data in 1-Port RAM IP Core

    learni, Aug 10, 2017
    Replies:
    0
    Views:
    663
    learni
    Aug 10, 2017
  18. afef

    How to write if statement written in matlab with vhdl ?

    afef, Jul 10, 2017
    Replies:
    0
    Views:
    552
    afef
    Jul 10, 2017
  19. avishay

    Converting VHDL to XML

    avishay, Jan 29, 2006
    Replies:
    4
    Views:
    3,665
    Fahad Majeed
    May 25, 2017
  20. akshata@94

    verilog, rtl, simulation

    [email protected], Apr 22, 2017
    Replies:
    0
    Views:
    752
    [email protected]
    Apr 22, 2017
  21. sandeepthi

    Reading an xml file in vhdl

    sandeepthi, Apr 21, 2017
    Replies:
    0
    Views:
    920
    sandeepthi
    Apr 21, 2017
  22. Ana

    need to count constants names in vhdl

    Ana, Apr 19, 2017
    Replies:
    0
    Views:
    1,064
    Ana
    Apr 19, 2017
  23. raag2c

    Verilog code for MD5 algorithm

    raag2c, Jan 6, 2007
    Replies:
    2
    Views:
    3,897
    akshata.j
    Apr 18, 2017
  24. KC1

    Comparing Inputs to Outputs Simon Game

    KC1, Apr 11, 2017
    Replies:
    0
    Views:
    825
    KC1
    Apr 11, 2017
  25. Kritika Bhardwaj

    Query related to division of 1.122 in mentioned code.

    Kritika Bhardwaj, Mar 21, 2017
    Replies:
    0
    Views:
    698
    Kritika Bhardwaj
    Mar 21, 2017
  26. shachi

    verilog hdl

    shachi, Mar 15, 2017
    Replies:
    0
    Views:
    766
    shachi
    Mar 15, 2017
  27. chiraz

    Illegal sequential statement (VHDL)

    chiraz, Feb 17, 2017
    Replies:
    0
    Views:
    990
    chiraz
    Feb 17, 2017
  28. alok das gupta

    lms algorithm code

    alok das gupta, Jan 5, 2017
    Replies:
    0
    Views:
    897
    alok das gupta
    Jan 5, 2017
  29. Larinayo

    Mixer-Unit on Altera DE2-115 Cyclone IV

    Larinayo, Dec 28, 2016
    Replies:
    0
    Views:
    875
    Larinayo
    Dec 28, 2016
  30. Alenx

    VHDL Subtraction two’s complement

    Alenx, Dec 13, 2016
    Replies:
    0
    Views:
    1,449
    Alenx
    Dec 13, 2016
  31. andys86498

    2 flip-flop synchronizer

    andys86498, Nov 13, 2016
    Replies:
    1
    Views:
    1,660
    netguy63
    Nov 23, 2016
  32. Zo Ki

    Xilinx ISE, expression not globally static inside generic map

    Zo Ki, Nov 22, 2016
    Replies:
    0
    Views:
    827
    Zo Ki
    Nov 22, 2016
  33. Anand P Paralkar

    ASIC RTL and FPGA RTL

    Anand P Paralkar, Apr 26, 2004
    Replies:
    2
    Views:
    8,285
    Yasir Khizar
    Nov 7, 2016
  34. Anwesa Roy

    How to use ufixed when it involves multiplication a number of times?(VHDL question)

    Anwesa Roy, Aug 22, 2016
    Replies:
    0
    Views:
    1,246
    Anwesa Roy
    Aug 22, 2016
  35. Razn_957

    Input ports in VHDL of type string and Boolean

    Razn_957, Aug 19, 2016
    Replies:
    0
    Views:
    1,474
    Razn_957
    Aug 19, 2016
  36. Rashnak

    Issue with simulation time - Modelsim PE Student 10.4

    Rashnak, Jun 21, 2016
    Replies:
    1
    Views:
    990
    Rashnak
    Jun 22, 2016
  37. miroslavasadov

    pls help me ; vhdl;

    miroslavasadov, Jun 21, 2016
    Replies:
    0
    Views:
    1,198
    miroslavasadov
    Jun 21, 2016
  38. Moh

    I need a VHDL code

    Moh, Jun 8, 2016
    Replies:
    0
    Views:
    1,314
    Moh
    Jun 8, 2016
  39. eladsolomon

    and operator overloading

    eladsolomon, Jun 4, 2016
    Replies:
    0
    Views:
    1,030
    eladsolomon
    Jun 4, 2016
  40. Ibra1950

    1:8 demux behavioral and structural modeling

    Ibra1950, Jun 2, 2016
    Replies:
    1
    Views:
    5,951
    Ibra1950
    Jun 3, 2016
  41. Gonzalo

    Floating point library RC

    Gonzalo, May 27, 2016
    Replies:
    0
    Views:
    1,026
    Gonzalo
    May 27, 2016
  42. vijay

    VHDL 2005, VHDL93 and FPHDL

    vijay, Sep 16, 2005
    Replies:
    3
    Views:
    1,580
    Gonzalo
    May 27, 2016
  43. kiran77

    Minimum period: No path found

    kiran77, Apr 30, 2016
    Replies:
    0
    Views:
    1,472
    kiran77
    Apr 30, 2016
  44. Anviori

    Shift left register using VHDL shift operator : sll trouble

    Anviori, Apr 13, 2016
    Replies:
    0
    Views:
    981
    Anviori
    Apr 13, 2016
  45. Bhakti Dedhia

    4 bit two flipflop sychronizer

    Bhakti Dedhia, Mar 29, 2016
    Replies:
    0
    Views:
    946
    Bhakti Dedhia
    Mar 29, 2016
  46. _Jaiko007

    FPGA for Frequency Divider

    _Jaiko007, Mar 28, 2016
    Replies:
    0
    Views:
    886
    _Jaiko007
    Mar 28, 2016
  47. mrunal

    geting error as unxpected symbol read: ". in array initialization

    mrunal, Mar 27, 2016
    Replies:
    0
    Views:
    891
    mrunal
    Mar 27, 2016
  48. keerthi_raj

    Is my port map syntax right???? i am not able to find the proper guidance for the error in any book

    keerthi_raj, Mar 19, 2016
    Replies:
    0
    Views:
    773
    keerthi_raj
    Mar 19, 2016
  49. jose de arimatea

    Send data from MATLAB to FPGA through USB

    jose de arimatea, Feb 3, 2016
    Replies:
    0
    Views:
    1,223
    jose de arimatea
    Feb 3, 2016
  50. rupakala

    vhdl

    rupakala, Jan 12, 2016
    Replies:
    0
    Views:
    1,147
    rupakala
    Jan 12, 2016
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