VHDL

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comp.lang.vhdl
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Some Cash for Vhdl coding
  • Harry12
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56
Harry12
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H
Vhdl coding
  • Harry12
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0
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49
Harry12
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R
Can anyone please help me in this code
  • ragerrani
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1
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97
TheAliceMay
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A
What is `transaction`event
  • Ash72
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0
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64
Ash72
A
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Low level block coding
  • Roger31415
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0
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62
Roger31415
R
C
VHDL code for multiplier
  • chi_rulez
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8
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23K
Hao
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A
What does 'genbin' and 'addbins' in OSVVM mean?
  • Ash72
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0
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77
Ash72
A
D
Binary to BCD code understanding
  • div_01
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0
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177
div_01
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N
Outputting signal values to terminal Within Character Array
  • new_guy_505
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0
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203
new_guy_505
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L
Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
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0
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507
Luis7910
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L
Lattice EFB I2C core works in simulation, but not on hardware
  • littlegamer
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3
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4K
lars555
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P
character to std_logic_vector
  • Pedro Claro
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8
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33K
furqhan
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M
Convert boolean to std_logic
  • manolis kaliorakis
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3
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25K
cube1us
C
N
VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
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0
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2K
Nikos_for_vhdl
N
A
Modelsim simulation Problem?
  • alexglvr
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3
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2K
GopikaCB
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VHDL multiplier
  • mk7899
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0
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1K
mk7899
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Register clear on read
  • kamalre
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0
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2K
kamalre
K
X
IC 74374-getting incorrect simulation
  • xorro
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0
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814
xorro
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D
2 JK Circuit in VHDL
  • dumdumdum
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0
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790
dumdumdum
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conv_std_logic_vector
  • trescot
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5
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27K
bala6007
B
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
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0
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841
ADHUL
A
V
Sum of element array
  • VHDL_HELP
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2
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1K
alireza95
A
A
sum of a array's element
  • alireza95
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0
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768
alireza95
A
A
reading binary file using vhdl
  • assaad EL Makhloufi
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0
Views
750
assaad EL Makhloufi
A
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
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0
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890
JaneJune
J
A
Problem With Mealy Sequence Detector
  • Armand
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1
Views
784
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
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0
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840
Cor
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
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1
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2K
Cor
C
L
LFSR doesn't generate random values during simulation
  • learni
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1
Views
921
Cor
C
L
Cannot Read Data in 1-Port RAM IP Core
  • learni
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0
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865
learni
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How to write if statement written in matlab with vhdl ?
  • afef
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0
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721
afef
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A
Converting VHDL to XML
  • avishay
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4
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4K
Fahad Majeed
Fahad Majeed
A
verilog, rtl, simulation
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0
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918
[email protected]
A
S
Reading an xml file in vhdl
  • sandeepthi
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0
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1K
sandeepthi
S
A
need to count constants names in vhdl
  • Ana
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0
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2K
Ana
A
R
Verilog code for MD5 algorithm
  • raag2c
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2
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4K
akshata.j
A
K
Comparing Inputs to Outputs Simon Game
  • KC1
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0
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998
KC1
K
K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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0
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887
Kritika Bhardwaj
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verilog hdl
  • shachi
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0
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933
shachi
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C
Illegal sequential statement (VHDL)
  • chiraz
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0
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1K
chiraz
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lms algorithm code
  • alok das gupta
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0
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1K
alok das gupta
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Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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0
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1K
Larinayo
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A
VHDL Subtraction two’s complement
  • Alenx
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0
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2K
Alenx
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A
2 flip-flop synchronizer
  • andys86498
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1
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2K
netguy63
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Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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0
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1K
Zo Ki
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ASIC RTL and FPGA RTL
  • Anand P Paralkar
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2
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9K
Yasir Khizar
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How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
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0
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1K
Anwesa Roy
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Input ports in VHDL of type string and Boolean
  • Razn_957
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0
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2K
Razn_957
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R
Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
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1
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1K
Rashnak
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miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
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0
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2K
miroslavasadov
miroslavasadov
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