VHDL

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comp.lang.vhdl
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VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
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0
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2K
Nikos_for_vhdl
N
A
Modelsim simulation Problem?
  • alexglvr
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3
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2K
GopikaCB
G
M
VHDL multiplier
  • mk7899
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0
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767
mk7899
M
K
Register clear on read
  • kamalre
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0
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1K
kamalre
K
X
IC 74374-getting incorrect simulation
  • xorro
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0
Views
608
xorro
X
D
2 JK Circuit in VHDL
  • dumdumdum
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0
Views
588
dumdumdum
D
T
conv_std_logic_vector
  • trescot
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5
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27K
bala6007
B
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
Replies
0
Views
631
ADHUL
A
V
Sum of element array
  • VHDL_HELP
Replies
2
Views
1K
alireza95
A
A
sum of a array's element
  • alireza95
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0
Views
596
alireza95
A
A
reading binary file using vhdl
  • assaad EL Makhloufi
Replies
0
Views
597
assaad EL Makhloufi
A
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
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0
Views
693
JaneJune
J
A
Problem With Mealy Sequence Detector
  • Armand
Replies
1
Views
638
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
Replies
0
Views
577
Cor
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
Replies
1
Views
2K
Cor
C
L
LFSR doesn't generate random values during simulation
  • learni
Replies
1
Views
687
Cor
C
L
Cannot Read Data in 1-Port RAM IP Core
  • learni
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0
Views
698
learni
L
A
How to write if statement written in matlab with vhdl ?
  • afef
Replies
0
Views
587
afef
A
A
Converting VHDL to XML
  • avishay
Replies
4
Views
4K
Fahad Majeed
Fahad Majeed
A
verilog, rtl, simulation
Replies
0
Views
784
[email protected]
A
S
Reading an xml file in vhdl
  • sandeepthi
Replies
0
Views
968
sandeepthi
S
A
need to count constants names in vhdl
  • Ana
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0
Views
1K
Ana
A
R
Verilog code for MD5 algorithm
  • raag2c
Replies
2
Views
4K
akshata.j
A
K
Comparing Inputs to Outputs Simon Game
  • KC1
Replies
0
Views
856
KC1
K
K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
Replies
0
Views
733
Kritika Bhardwaj
K
S
verilog hdl
  • shachi
Replies
0
Views
794
shachi
S
C
Illegal sequential statement (VHDL)
  • chiraz
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0
Views
1K
chiraz
C
A
lms algorithm code
  • alok das gupta
Replies
0
Views
927
alok das gupta
A
L
Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
Replies
0
Views
911
Larinayo
L
A
VHDL Subtraction two’s complement
  • Alenx
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0
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2K
Alenx
A
A
2 flip-flop synchronizer
  • andys86498
Replies
1
Views
2K
netguy63
N
Z
Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
Replies
0
Views
859
Zo Ki
Z
A
ASIC RTL and FPGA RTL
  • Anand P Paralkar
Replies
2
Views
8K
Yasir Khizar
Y
A
How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
Replies
0
Views
1K
Anwesa Roy
A
R
Input ports in VHDL of type string and Boolean
  • Razn_957
Replies
0
Views
2K
Razn_957
R
R
Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
Replies
1
Views
1K
Rashnak
R
miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
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0
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1K
miroslavasadov
miroslavasadov
M
I need a VHDL code
  • Moh
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0
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1K
Moh
M
E
and operator overloading
  • eladsolomon
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0
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1K
eladsolomon
E
I
1:8 demux behavioral and structural modeling
  • Ibra1950
Replies
1
Views
6K
Ibra1950
I
G
Floating point library RC
  • Gonzalo
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0
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1K
Gonzalo
G
V
VHDL 2005, VHDL93 and FPHDL
  • vijay
Replies
3
Views
2K
Gonzalo
G
K
Minimum period: No path found
  • kiran77
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0
Views
2K
kiran77
K
A
Shift left register using VHDL shift operator : sll trouble
  • Anviori
Replies
0
Views
1K
Anviori
A
B
4 bit two flipflop sychronizer
  • Bhakti Dedhia
Replies
0
Views
978
Bhakti Dedhia
B
J
FPGA for Frequency Divider
  • _Jaiko007
Replies
0
Views
925
_Jaiko007
J
M
geting error as unxpected symbol read: ". in array initialization
  • mrunal
Replies
0
Views
928
mrunal
M
K
  • Poll
Is my port map syntax right???? i am not able to find the proper guidance for the error in any book
  • keerthi_raj
Replies
0
Views
805
keerthi_raj
K
J
Send data from MATLAB to FPGA through USB
  • jose de arimatea
Replies
0
Views
1K
jose de arimatea
J
R
vhdl
  • rupakala
Replies
0
Views
1K
rupakala
R
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