VHDL

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comp.lang.vhdl
H
VHDL: AXI-stream FIFO
  • HMSStanley
Replies
2
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266
HMSStanley
H
A
How does a HEAD pointer end up pointing to the first node in a linked list?
  • Ash72
Replies
3
Views
116
Ash72
A
H
real number to 16 bit signed number
  • hari
Replies
7
Views
14K
saket.sona
S
S
New to VHDL... Trying to convert a 2-bytes number into an decimal
  • ST3005
Replies
0
Views
112
ST3005
S
G
Piotrowski, Walt,
  • God1989
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0
Views
113
God1989
G
L
Reed solomon decoder issue
  • lokeshvayala
Replies
0
Views
149
lokeshvayala
L
B
Clock divide by 5
  • blesssy
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0
Views
154
blesssy
B
Q
How to check time delay caused by code itself?
  • Quuruu
Replies
1
Views
170
Quuruu
Q
H
Some Cash for Vhdl coding
  • Harry12
Replies
0
Views
197
Harry12
H
H
Vhdl coding
  • Harry12
Replies
0
Views
182
Harry12
H
R
Can anyone please help me in this code
  • ragerrani
Replies
1
Views
255
TheAliceMay
T
A
What is `transaction`event
  • Ash72
Replies
0
Views
183
Ash72
A
R
Low level block coding
  • Roger31415
Replies
0
Views
187
Roger31415
R
C
VHDL code for multiplier
  • chi_rulez
Replies
8
Views
23K
Hao
H
A
What does 'genbin' and 'addbins' in OSVVM mean?
  • Ash72
Replies
0
Views
228
Ash72
A
D
Binary to BCD code understanding
  • div_01
Replies
0
Views
472
div_01
D
N
Outputting signal values to terminal Within Character Array
  • new_guy_505
Replies
0
Views
457
new_guy_505
N
L
Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
Replies
0
Views
687
Luis7910
L
L
Lattice EFB I2C core works in simulation, but not on hardware
  • littlegamer
Replies
3
Views
5K
lars555
L
P
character to std_logic_vector
  • Pedro Claro
Replies
8
Views
34K
furqhan
F
M
Convert boolean to std_logic
  • manolis kaliorakis
Replies
3
Views
29K
cube1us
C
N
VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
Replies
0
Views
2K
Nikos_for_vhdl
N
A
Modelsim simulation Problem?
  • alexglvr
Replies
3
Views
3K
GopikaCB
G
M
VHDL multiplier
  • mk7899
Replies
0
Views
1K
mk7899
M
K
Register clear on read
  • kamalre
Replies
0
Views
2K
kamalre
K
X
IC 74374-getting incorrect simulation
  • xorro
Replies
0
Views
979
xorro
X
D
2 JK Circuit in VHDL
  • dumdumdum
Replies
0
Views
937
dumdumdum
D
T
conv_std_logic_vector
  • trescot
Replies
5
Views
28K
bala6007
B
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
Replies
0
Views
984
ADHUL
A
V
Sum of element array
  • VHDL_HELP
Replies
2
Views
1K
alireza95
A
A
sum of a array's element
  • alireza95
Replies
0
Views
925
alireza95
A
A
reading binary file using vhdl
  • assaad EL Makhloufi
Replies
0
Views
887
assaad EL Makhloufi
A
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
Replies
0
Views
1K
JaneJune
J
A
Problem With Mealy Sequence Detector
  • Armand
Replies
1
Views
919
Cor
C
C
How to get signal name as a string in a procedure?
  • Cor
Replies
0
Views
1K
Cor
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
Replies
1
Views
3K
Cor
C
L
LFSR doesn't generate random values during simulation
  • learni
Replies
1
Views
1K
Cor
C
L
Cannot Read Data in 1-Port RAM IP Core
  • learni
Replies
0
Views
972
learni
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A
How to write if statement written in matlab with vhdl ?
  • afef
Replies
0
Views
834
afef
A
A
Converting VHDL to XML
  • avishay
Replies
4
Views
4K
Fahad Majeed
Fahad Majeed
A
verilog, rtl, simulation
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0
Views
1K
[email protected]
A
S
Reading an xml file in vhdl
  • sandeepthi
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0
Views
1K
sandeepthi
S
A
need to count constants names in vhdl
  • Ana
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0
Views
2K
Ana
A
R
Verilog code for MD5 algorithm
  • raag2c
Replies
2
Views
4K
akshata.j
A
K
Comparing Inputs to Outputs Simon Game
  • KC1
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0
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1K
KC1
K
K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
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0
Views
1K
Kritika Bhardwaj
K
S
verilog hdl
  • shachi
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0
Views
1K
shachi
S
C
Illegal sequential statement (VHDL)
  • chiraz
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0
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2K
chiraz
C
A
lms algorithm code
  • alok das gupta
Replies
0
Views
1K
alok das gupta
A
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Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
Replies
0
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1K
Larinayo
L
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