Query related to division of 1.122 in mentioned code.

Discussion in 'VHDL' started by Kritika Bhardwaj, Mar 21, 2017.

  1. Kritika Bhardwaj

    Kritika Bhardwaj

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    -- Divide a 24 bits unsigned by 1.122
    -- Author : Bert Cuzeau
    -- not overly optimized (yet under 150 LCs of plain logic)

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;

    -- ---------------------------------------
    Entity DIVBYR is -- Divide a 24 bits by 1.122
    -- ---------------------------------------
    Port ( Clk : In std_logic; -- Main System Clock
    Rst : In std_logic; -- Asynchronous reset, active high
    D : in unsigned (23 downto 0); -- use std_logic_vector !
    Q : out unsigned (23 downto 0) -- use std_logic_vector !
    ); --
    end;

    -- ---------------------------------------
    Architecture RTL of DIVBYR is
    -- ---------------------------------------
    begin

    process (Rst,Clk)
    begin
    if Rst='1' then
    Q <= (others=>'0');
    elsif rising_edge (Clk) then
    Q <= to_unsigned( (to_integer(D) * 7301 / 8192 ),24);
    end if;
    end process;

    end RTL;

    In above code, why 7301/8192 is used instead of 1.122?
     
    Kritika Bhardwaj, Mar 21, 2017
    #1
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