Help code VHDL


A

Ayoub

hi everybody !

I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data

and the result would be S .

Can you help me correcting this code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Premier is
port(
clk:in std_logic ;
rst:in std_logic ;
data:in std_logic ;
CD :in std_logic_vector(3 downto 0);
S :eek:ut std_logic );
end entity ;

architecture beh of Premier is

signal i :integer range 0 to 3;
signal iCD :std_logic_vector(3 downto 0);
signal idata:std_logic ;

begin

code:process(clk,rst)
begin
if(rst='1') then
S<='0';
i<=0;
idata<=data ;
iCD <=CD ;
else
if(clk'event and clk='1')then

if(CD(0)='0')then
iCD(3 downto 0)<="1111";
else
iCD(3 downto 0)<="0001";
end if ;

if(CD(1)='0') then
iCD(3 downto 0)<="1111";
else
iCD(3 downto 0)<="0001";
end if ;

if(CD(2)='0') then
iCD(3 downto 0)<="1111";
else
iCD(3 downto 0)<="0001";

end if ;

if(CD(3)='0') then
iCD(3 downto 0)<="1111";
else
iCD(3 downto 0)<="0001";
end if ;

S<=not(iCD(i) xor (idata));
i<= i+1;

if i=3 then
idata<= data ;
end if ;
end if ;
end if ;
end process ;

end architecture ;

Thank you !
 
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J

John Speth

I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data
and the result would be S .

According to my interpretation of the stated requirements, this pseudo
code should work:

func([in] CD, [in] data, [out] S)
if CD == 0
S = -1
else if CD == 1
S = 1
else
S = CD + data
func end

No registers or clocking are needed. It is basic combinatorial logic.

JJS
 
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A

Ayoub

I want to convert 0 to -1 and 1 to 1 after that I would like to add CD with data
and the result would be S .



According to my interpretation of the stated requirements, this pseudo

code should work:



func([in] CD, [in] data, [out] S)

if CD == 0

S = -1

else if CD == 1

S = 1

else

S = CD + data

func end



No registers or clocking are needed. It is basic combinatorial logic.



JJS

Thank you very much ^^
 

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