A
Ayoub
Hello!
In fact,i have a small problem but I don't understand what I should do
here is my code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed .all ;
entity M is
port(
clk : in std_logic ;
rst : in std_logic ;
data : in std_ulogic_vector(1 downto 0);
CD : in std_logic_vector(3 downto 0);
s : out std_logic_vector (1 downto 0));
end entity ;
architecture beh of M is
signal com :std_logic_vector(3 downto 0);
begin
code
rocess(clk,rst)
begin
if (rst='1') then
(others=>'0')<=data;
--data<='0' !!! ;
(others=>'0')<=CD;
--"0000"<=CD ;
s <=(others=>'0');
else
for i in 0 to 3 loop
if (clk'event and clk='1')then
--for i in 0 to 3 loop
com(i)<= not(CD(i) xor data) ;
end if ;
end loop ;
end if ;
end process ;
s<=com(i) ;
end architecture ;
This is my problem :
"""Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type"""
Thanks in advanced.
In fact,i have a small problem but I don't understand what I should do
here is my code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed .all ;
entity M is
port(
clk : in std_logic ;
rst : in std_logic ;
data : in std_ulogic_vector(1 downto 0);
CD : in std_logic_vector(3 downto 0);
s : out std_logic_vector (1 downto 0));
end entity ;
architecture beh of M is
signal com :std_logic_vector(3 downto 0);
begin
code
begin
if (rst='1') then
(others=>'0')<=data;
--data<='0' !!! ;
(others=>'0')<=CD;
--"0000"<=CD ;
s <=(others=>'0');
else
for i in 0 to 3 loop
if (clk'event and clk='1')then
--for i in 0 to 3 loop
com(i)<= not(CD(i) xor data) ;
end if ;
end loop ;
end if ;
end process ;
s<=com(i) ;
end architecture ;
This is my problem :
"""Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type"""
Thanks in advanced.