erreur VHDL

A

Ayoub

Hello!

In fact,i have a small problem but I don't understand what I should do

here is my code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed .all ;

entity M is
port(
clk : in std_logic ;
rst : in std_logic ;
data : in std_ulogic_vector(1 downto 0);
CD : in std_logic_vector(3 downto 0);
s : out std_logic_vector (1 downto 0));

end entity ;

architecture beh of M is

signal com :std_logic_vector(3 downto 0);

begin

code :process(clk,rst)

begin

if (rst='1') then
(others=>'0')<=data;
--data<='0' !!! ;
(others=>'0')<=CD;
--"0000"<=CD ;
s <=(others=>'0');
else
for i in 0 to 3 loop

if (clk'event and clk='1')then

--for i in 0 to 3 loop

com(i)<= not(CD(i) xor data) ;

end if ;
end loop ;

end if ;
end process ;
s<=com(i) ;
end architecture ;

This is my problem :

"""Error (10476): VHDL error at M.vhd(38): type of identifier "data" does not agree with its usage as "std_ulogic" type"""


Thanks in advanced.
 
T

Tobias Baumann

Am 06.05.2014 15:41, schrieb Ayoub:
com(i)<= not(CD(i) xor data) ;

Check this line. What type/size has data and compare it with type/size
of CD(i).

Tobias
 
S

Sean Durkin

Hi Ayoub,
Hello!

In fact,i have a small problem but I don't understand what I should do
there's a few problems that should cause compilation errors, not only one.
here is my code:

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed .all ;
Get used to never using ieee.std_logic_signed.all. Use
ieee.numeric_std.all instead and use the signed/unsigned types as needed.
entity M is
port(
clk : in std_logic ;
rst : in std_logic ;
data : in std_ulogic_vector(1 downto 0);
CD : in std_logic_vector(3 downto 0);
s : out std_logic_vector (1 downto 0));

end entity ;

architecture beh of M is

signal com :std_logic_vector(3 downto 0);

begin

code :process(clk,rst)

begin

if (rst='1') then
(others=>'0')<=data;
This line should cause an error, too. Delete it, it doesn't make sense.
(others=>'0') is not a signal you can assign something to.
--data<='0' !!! ;
(others=>'0')<=CD;
See above.

It looks like you're trying to clear "data" and "CD" here in reset. You
cannot do that, since both "data" and "CD" are inputs to your entity,
meaning they are generated OUTSIDE of your module; hence you have no way
of influencing their values. If you want to clear them, you need to do
that in another module that connects to yours or a testbench that
instantiates this module and drives its inputs.
--"0000"<=CD ;
s <=(others=>'0');
else
for i in 0 to 3 loop

if (clk'event and clk='1')then
.... the "for" loop should be outside the clock condition. Otherwise
you'd basically have 4 clock conditions. Not sure what simulation and
synthesis tools would do with that. It's legal VHDL, but makes no sense
in practice.
--for i in 0 to 3 loop

com(i)<= not(CD(i) xor data) ;

end if ;
end loop ;

end if ;
end process ;
s<=com(i) ;
There's another bunch of problems here...
- You have two sources for signal "s". It is assigned inside your
process and outside of it. When you synthesize this, you'll probably get
a "multiple drivers" error.
- You use the i-index that is only known inside the process.
- com(i) is of length 1, s is of length 2, so the assignment won't work
here, anyway...

Same applies to "com(i)<= not(CD(i) xor data) ;". Data is of length 2,
so you can't xor it with a single bit.

I'm surprised the first thing your simulation tool finds is the problem
in line 38...

I don't know what you are trying to do, so I can't tell you what to do
exactly, but first I suggest you get a book on VHDL or read up on the
web. You seem to lack basic understanding of the language constructs...

HTH,
Sean
 

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