Illegal sequential statement (VHDL)

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Feb 17, 2017
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Hi all,
I am new in VHDL, this is my code and the error is illegal sequential statement ,can you help me please ?
thank you



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package my_package is
constant K: integer := 6;
constant l:integer:=11;
end my_package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;
entity reduction is
port(
n : IN STD_LOGIC_VECTOR(k DOWNTO 0);
z : IN STD_LOGIC_VECTOR(l DOWNTO 0);
r : OUT STD_LOGIC_VECTOR(l DOWNTO 0)
);
end reduction;
architecture arch of reduction is
signal k, l : integer ;
signal less_out, equal_out,greater_out: STD_LOGIC;
signal e,s,x,m,sortie1,h1: STD_LOGIC_VECTOR(11 DOWNTO 0);
signal t,a: STD_LOGIC_VECTOR(6 DOWNTO 0);
Type myTab_type is array (6 downto 0) of STD_LOGIC_VECTOR(6 DOWNTO 0) ;
SIGNAL tab : myTab_type := ("0011111","0111110","0011011","0110110","0001011","0010110","0101100") ;
signal less, equal,greater : STD_LOGIC;
component comparaison
port(
num1 : in std_logic_vector(11 downto 0);
num2 : in std_logic_vector(11 downto 0);
less : out std_logic;
equal : out std_logic;
greater : out std_logic
);
END COMPONENT;
component Add_SubMOD
port(
x, y: in std_logic_vector(K-1 downto 0);
addb_sub: in std_logic;
z: out std_logic_vector(K-1 downto 0)
);
END COMPONENT;
BEGIN
process(z,n)
begin
e<=z;
t<=n;
k<=t'length;
l<=e'length;
s<="00000" & t;
c0:comparaison port map (e(11 downto 0),s(11 downto 0),less_out, equal_out,greater_out);
if (less_out='1') then
x<=e;
end if;
if (l=k) then
c1:Add_SubMOD port map (e(11 downto 0),s(11 downto 0),'1',x);
end if;
x<="000000000000";
g1: for i in (l-1) downto k loop
if (e(i) = '1') then
h1<= "00000" & tab(i);
c2:Add_SubMOD port map (x(11 downto 0),h1(11 downto 0),'0',x);
end if;
end loop;
g2: for j in 0 to (k-1) loop
a(j) <= e(j);
m<="00000" & a;
c3:Add_SubMOD port map (x(11 downto 0),m(11 downto 0),'0',x);
end loop;
while (x>=e) loop
-- x<=x-e;
c4:Add_SubMOD port map (x(11 downto 0),s(11 downto 0),'1',x);
end loop;
while (x< 0) loop
-- x<=x+e;
c5:Add_SubMOD port map (x(11 downto 0),s(11 downto 0),'0',x);
end loop;
r<=x;
end process;
end arch;
 

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