geting error as unxpected symbol read: ". in array initialization

Discussion in 'VHDL' started by mrunal, Mar 27, 2016.

  1. mrunal

    mrunal

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    Hello,
    I am implementing VHDL code for chien search error evaluator in Reed Solomon decoder.
    I am facing error as unxpected symbol read: ". in intialization of 2D memory and 1D index arrary.
    Expecting help in this scenario.
    Regards,
    Mrunal.


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity csee is
    Port ( clk: in STD_LOGIC;
    elp : in STD_LOGIC_VECTOR (71 downto 0);
    evp : in STD_LOGIC_VECTOR (63 downto 0);
    ev : out STD_LOGIC_VECTOR (7 downto 0));
    end csee;
    architecture Behavioral of csee is
    Component gfmul8 is
    Port ( IP6: in STD_LOGIC_VECTOR (7 downto 0);
    IP7: in STD_LOGIC_VECTOR (7 downto 0);
    OP4: out STD_LOGIC_VECTOR (7 downto 0));
    end component;
    component DFF is
    Port ( clk:in STD_LOGIC;
    IP1: in STD_LOGIC_VECTOR (7 downto 0);
    OP1: out STD_LOGIC_VECTOR (7 downto 0));
    end component;
    component mux is
    Port ( clk:in STD_LOGIC;
    Data0 : in STD_LOGIC_VECTOR (7 downto 0);
    Data1 : in STD_LOGIC_VECTOR (7 downto 0);
    sel : in bit;
    yout: out STD_LOGIC_VECTOR (7 downto 0));
    end component;

    signal csee_ready: bit:='1';
    signal even: std_logic_vector(7 downto 0);
    signal odd: std_logic_vector(7 downto 0);
    signal zdop: std_logic_vector(7 downto 0);
    signal iop: std_logic_vector(7 downto 0);
    signal x: std_logic_vector(7 downto 0);
    signal x1: std_logic_vector(7 downto 0);
    signal oddx:integer;
    signal oddy:integer;

    signal dop0,dop1,dop2,dop3,dop4,dop5,dop6,dop7,dop8,dop9,dop10,dop11,dop12,dop13,dop14,dop15,dop16: STD_LOGIC_VECTOR(7 downto 0) :="00000000";
    signal yout0,yout1,yout2,yout3,yout4,yout5,yout6,yout7,yout8,yout9,yout10,yout11,yout12,yout13,yout14,yout15,yout16:STD_LOGIC_VECTOR(7 downto 0) :="00000000";
    signal din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11,din12,din13,din14,din15,din16 :STD_LOGIC_VECTOR(7 downto 0) :="00000000";
    signal sig:STD_LOGIC_VECTOR(7 downto 0);
    type memory is array(0 to 15,0 to 15)of STD_LOGIC_VECTOR(7 downto 0);
    signal ptr3:memory:=ptr3<=((x”"00"“,x”"01“",x"”8D"“,x"”F6"“,x"”CB“",x"”52“",x”"7B“",x"”D1"“,x”"E8"“,x”"4F"“,x"”29",x"”C0"“,x”"B0"“,x"”E1"“,x"”E5"“,x”"C7“"),
    (x"”74"“,x”"B4"“,x"”AA"“,x”"4B"“,x”"99“",x”"2B"“,x”"60"“,x”"5F"“,x”"58"“,x"”3F"“,x"”FD"“,x”"CC"“,x”"FF"“,x”"40“",x"”EE"“,x”"B2“"),
    (x”"3A"“,x"”6E“",x"”5A"“,x"”F1"“,x"”55"“,x”"4D“",x”"A8"“,x"”C9“",x"”C1"“,x”"0A"“,x”"98"“,x”"15"“,x”"30“",x"”44"“,x”"A2"“,x"”C2")“,
    (x"”2C"“,x”"45"“,x"”92“",x"”6C"“,x”"F3"“,x”"39"“,x”"66“",x”"42"“,x”"F2"“,x”"35"“,x”"20“",x”"6F"“,x”"77"“,x”"BB"“,x”"59"“,x”"19"“),
    (x"”1D"“,x"”FE"“,x”"37"“,x"”67“",x"”2D“",x”"31"“,x”"F5"“,x”"69“",x"”A7"“,x”"64“",x"”AB"“,x”"13“",x”"54“",x"”25"“,x”"C9"“,x"”09")“,
    (x”"ED“",x”"5C"“,x”"05"“,x”"CA"“,x”"4C"“,x"”24“",x"”87"“,x"”BF"“,x"”18"“,x”"3E“",x”"22“",x"”F0"“,x"”51“",x”"EC"“,x”"61"“,x”"17“"),
    (x”"16"“,x"”5E“",x"”AF"“,x”"D3"“,x”"49"“,x"”A6“",x"”36"“,x”"43“",x”"F4"“,x"”47"“,x"”91"“,x”"DF“",x"”33“",x"”93"“,x”"21“",x”"3B“"),
    (x"”79"“,x”"B7"“,x”"97“",x”"85“",x"”10"“,x”"B5"“,x”"BA“",x”"3C“",x"”B6"“,x”"70"“,x"”D0“",x”"06"“,x"”A1"“,x"”FA“",x”"81“",x”"82“"),
    (x"”83“",x”"7E"“,x”"7F"“,x”"80“",x”"96"“,x”"73"“,x"”BE"“,x”"56“",x”"9B“",x"”9E“",x"”95“",x"”D9"“,x”"F7“",x”"02"“,x"”B9"“,x”"A4“"),
    (x”"DE"“,x”"6A"“,x”"32"“,x”"6D“",x”"D8“",x”"8A“",x"”84“",x”"72“",x”"2A“",x”"14"“,x”"9F“",x”"88"“,x”"F9"“,x"”DC“",x”"89“",x”"9A“"),
    (x”"FB"“,x”"7C“",x”"2E"“,x”"C3"“,x"”8F"“,x"”B8"“,x"”65“",x”"48"“,x"”26“",x"”C8"“,x”"12"“,x”"4A“",x"”CE“",x"”E7“",x"”D2"“,x"”62"“),
    (x"”0C“",x"”E0"“,x”"1F“",x"”EF"“,x”"11"“,x”"75"“,x”"78“",x”"71"“,x"”A5“",x”"8E"“,x”"76"“,x”"3D“",x"”BD“",x"”BC"“,x”"86"“,x”"57)“,
    (x”"0B"“,x”"28“",x”"2F“",x"”A3"“,x”"DA“",x"”D4"“,x"”E4“",x”"0F“",x”"A9“",x”"27"“,x"”53“",x”"04“",x”"1B“",x"”FC“",x"”AC"“,x”"E6")“,
    (x”"7A“",x”"07"“,x"”AE“",x”"63"“,x"”C5"“,x"”DB“",x"”E2"“,x”"EA"“,x"”94“",x"”8B"“,x"”C4“",x"”D5"“,x”"9D“",x"”F8"“,x”"90"“,x”"6B“"),
    (x"”B1"“,x"”0D“",x"”D6“",x"”EB"“,x”"C6"“,x"”0E"“,x”"CF"“,x”"AD“",x”"08"“,x”"4E“",x"”D7"“,x”"E3"“,x”"5D“",x”"50“",x”"1E“",x”"B3“"),
    (x”"5B"“,x”"23"“,x”"38“",x”"34"“,x”"68"“,x”"46“",x”"03"“,x”"8C"“,x”"DD“",x”"9C“",x”"7D“",x"”A0"“,x”"CD“",x”"1A"“,x”"41“",x”"1C“"));


    type index is array(0 to 254)of STD_LOGIC_VECTOR(7 downto 0);
    signal ptr6:index:=(x”"01"“,x”"02",x"”04"“,x"”08"“,x"10”“",x"20”“",x”"“40",x"80"“,x”"1D"“,x”"3A"“,x"74",x"E8"“,x”"CD"“,x"87"“,x"13"“,x”"26“",
    x"4C”"“,x”"98"“,x"2D"“,x”"5A"“,x”"B4“",x”"75"“,x”"DA"“,x”"C9"“,x”"8F"“,x"03”"“,x"06”"“,x”"0C"“,x”"18"“,x”"30“",x"60”"“,x”"“C0",
    x”"9D"“,x"27”“",x"”4E"“,x"9C”"“,x"25"“,x”"4A“",x”"94"“,x"35”“",x"6A”"“,x”"D4"“,x”"B5"“,x”"77"“,x”"“EE",x"”C1"“,x”"9F"“,x"23”"“,
    x"46”"“,x”"8C"“,x"05”“",x"0A"“,x”"14"“,x”"28"“,x”"50“",x”"A0"“,x”"5D"“,x”"BA"“,x”"69“",x”"D2"“,x”"B9"“,x”"6F"“,x”"D7"“,x”"A1"“,
    x"5F”"“,x"BE”"“,x”"61"“,x"”“C2",x"99”“",x”"2F"“,x”"5E"“,x”"“BC",x"65”"“,x”"CA“",x"89”"“,x”"“0F",x”"1E“",x"”3C"“,x”"78"“,x"”F0"“,
    x”"FD“",x”"E7"“,x”"D3"“,x”"BB"“,x”"6B"“,x"DC”“",x"B1”"“,x"7F”"“,x"FE”"“,x”"E1“",x”"“DF",x"A3”"“,x"”“5B",x”"B6"“,x”"71"“,x”"E2“",
    x”"D9"“,x"AF”“",x"”43"“,x”"86"“,x”"11"“,x"22”“",x"44”"“,x”"88“",x”"0D"“,x"1A”"“,x"34”"“,x”"68“",x"D0”“",x"”BD"“,x”"“67",x”"“CE",
    x"81”"“,x”"1F"“,x”"“3E",x”"“7C",x"F8”"“,x”"ED"“,x”"C7“",x”"93“",x"3D”"“,x”"76"“,x"”“EC",x”"C5"“,x"97”"“,x"33”“",x”"66“",x”"“CC",
    x"85”“",x”"17"“,x”"2E"“,x”"“5C",x”"B8"“,x”"6D"“,x"”DA"“,x”"A9“",x”"4F“",x"9E”“",x"21”“",x"”42"“,x”"84“",x”"15"“,x"2A”"“,x”"“54",
    x”"A8"“,x”"4D"“,x”"9A"“,x”"29“",x”"“52",x”"A4“",x"55”“",x”"“AA",x”"49“",x”"92"“,x”"39“",x”"72"“,x”"E4"“,x"D5”“",x”"“B7",x”"“73",
    x”"E6"“,x”"D1“",x”"BF"“,x”"63"“,x"C6”"“,x"91”"“,x"”“3F",x”"7E"“,x"FC”“",x"E5”"“,x”"D7"“,x”"B3“",x"7B”“",x"”“F6",x"F1”"“,x"FF”"“,
    x"E3”“",x"”DB"“,x”"“AB",x"4B”"“,x”"96"“,x”"31"“,x”"62“",x”"C4"“,x"95”“",x”"37"“,x”"6E"“,x”"“DC",x"A5”“",x"”57"“,x”"AE"“,x”"41“",
    x”"82"“,x”"19“",x”"32“",x"C4”"“,x”"C8“",x"8D”"“,x"07”“",x”"0E“",x”"1C“",x”"38"“,x"70”“",x”"“E0",x”"“DD",x"A7”“",x"53”"“,x”"A6"“,
    x”"51“",x”"A2"“,x"59”“",x”"B2"“,x"79”"“,x"F2”“",x"F9”"“,x”"EF"“,x"C3”“",x"9B”"“,x"2B”“",x"56”"“,x”"AC“",x"”45"“,x”"8A"“,x”"05“",
    x"”12"“,x"23”“",x"48”“",x"90”"“,x”"3D"“,x"7A”"“,x”"F4"“,x”"F5“",x”"F7"“,x”"“F3",x"”FB"“,x”"EB"“,x”"CB“",x”"“8B",x”"0B“",x”"1C",
    x”"2C"“,x”"58"“,x”"“B0",x”"FD"“,x”"FA"“,x”"E9“",x”"F"“,x”"83"“,x”"“1B",x”"36“",x”"6C“",x"D8”"“,x”"AD“",x”"47"“,x”"“8E");

    begin
    mux_0: mux port map(clk,dop0,elp(71 downto 64),csee_ready,yout0);
    mux_1: mux port map(clk,dop1,elp(63 downto 56),csee_ready,yout1);
    mux_2: mux port map(clk,dop2,elp(55 downto 48),csee_ready,yout2);
    mux_3: mux port map(clk,dop3,elp(47 downto 40),csee_ready,yout3);
    mux_4: mux port map(clk,dop4,elp(39 downto 32),csee_ready,yout4);
    mux_5: mux port map(clk,dop5,elp(31 downto 24),csee_ready,yout5);
    mux_6: mux port map(clk,dop6,elp(23 downto 16),csee_ready,yout6);
    mux_7: mux port map(clk,dop7,elp(15 downto 8),csee_ready,yout7);
    mux_8: mux port map(clk,dop8,elp(7 downto 0),csee_ready,yout8);
    gfmul8_16: gfmul8 port map(yout0,sig,din0);
    gfmul8_17: gfmul8 port map(yout1,sig,din1);
    gfmul8_18: gfmul8 port map(yout2,sig,din2);
    gfmul8_19: gfmul8 port map(yout3,sig,din3);
    gfmul8_20: gfmul8 port map(yout4,sig,din4);
    gfmul8_21: gfmul8 port map(yout5,sig,din5);
    gfmul8_22: gfmul8 port map(yout6,sig,din6);
    gfmul8_23: gfmul8 port map(yout7,sig,din7);
    gfmul8_24: gfmul8 port map(yout8,sig,din8);
    DFF_16: DFF port map(clk,din0,dop0);
    DFF_17: DFF port map(clk,din1,dop1);
    DFF_18: DFF port map(clk,din2,dop2);
    DFF_19: DFF port map(clk,din3,dop3);
    DFF_20: DFF port map(clk,din4,dop4);
    DFF_21: DFF port map(clk,din5,dop5);
    DFF_22: DFF port map(clk,din6,dop6);
    DFF_23: DFF port map(clk,din7,dop7);
    DFF_24: DFF port map(clk,din8,dop8);
    even<=dop0 xor dop2 xor dop4 xor dop6 xor dop8;
    odd<=dop1 xor dop3 xor dop5 xor dop7;
    zdop<= not(even xor odd);
    oddx<=conv_integer(odd(7 downto 4));
    oddy<=conv_integer(odd(3 downto 0));
    iop<=ptr3(oddx,oddy);
    mux_9: mux port map(clk,dop9,evp(63 downto 56),csee_ready,yout9);
    mux_10: mux port map(clk,dop10,evp(55 downto 48),csee_ready,yout10);
    mux_11: mux port map(clk,dop11,evp(47 downto 40),csee_ready,yout11);
    mux_12: mux port map(clk,dop12,evp(39 downto 32),csee_ready,yout12);
    mux_13: mux port map(clk,dop13,evp(31 downto 24),csee_ready,yout13);
    mux_14: mux port map(clk,dop14,evp(23 downto 16),csee_ready,yout14);
    mux_15: mux port map(clk,dop15,evp(15 downto 8),csee_ready,yout15);
    mux_16: mux port map(clk,dop16,evp(7 downto 0),csee_ready,yout16);

    gfmul8_25: gfmul8 port map(yout9,"00000001",din9);
    gfmul8_26: gfmul8 port map(yout10,"00000010",din10);
    gfmul8_27: gfmul8 port map(yout11,"00000100",din11);
    gfmul8_28: gfmul8 port map(yout12,"00001000",din12);
    gfmul8_29: gfmul8 port map(yout13,"00010000",din13);
    gfmul8_30: gfmul8 port map(yout14,"00100000",din14);
    gfmul8_31: gfmul8 port map(yout15,"01000000",din15);
    gfmul_32: gfmul8 port map(yout16,"10000000",din16);

    DFF_25: DFF port map(clk,din9,dop9);
    DFF_26: DFF port map(clk,din10,dop10);
    DFF_27: DFF port map(clk,din11,dop11);
    DFF_28: DFF port map(clk,din12,dop12);
    DFF_29: DFF port map(clk,din13,dop13);
    DFF_30: DFF port map(clk,din14,dop14);
    DFF_31: DFF port map(clk,din15,dop15);
    DFF_32: DFF port map(clk,din16,dop16);
    x<=dop9 xor dop10 xor dop11 xor dop12 xor dop13 xor dop14 xor dop15 xor dop16;
    gfmul_33: gfmul8 port map(iop,x,x1);
    ev<=x1 and zdop;
    process
    variable count4:integer range 255 downto 0;
    begin

    loop6:while count4>0 loop
    wait until (clk ='1')and clk'event;
    count4:=count4-1;
    sig<=ptr6(count4);
    end loop loop6;
    end process;

    end Behavioral;
     
    mrunal, Mar 27, 2016
    #1
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