pls help me ; vhdl;

Joined
Jun 21, 2016
Messages
1
Reaction score
0
hello.
pls help me
I cant solve the problem:(:(:(:(
my code is:
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:33:46 06/05/2016
-- Design Name:
-- Module Name: C:/Users/Hossein/Desktop/fault_adder/v1/test_bench.vhd
-- Project Name: v1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fault_module_v3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
--LIBRARY ieee;
--USE ieee.std_logic_1164.ALL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test_bench IS
END test_bench;

ARCHITECTURE behavior OF test_bench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fault_module_v3
PORT(
CLK : IN std_logic;
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
S2 : IN std_logic;
S3 : IN std_logic;
S4 : IN std_logic;
S5 : IN std_logic;
S6 : IN std_logic;
S7 : IN std_logic;
S8 : IN std_logic;
S9 : IN std_logic;
random_num : out std_logic_vector (9 downto 0);
Error : OUT std_logic
);
END COMPONENT;


--Inputs
signal CLK : std_logic := '0';
signal A : std_logic := '0';
signal B : std_logic := '0';
signal Cin : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
signal S2 : std_logic := '0';
signal S3 : std_logic := '0';
signal S4 : std_logic := '0';
signal S5 : std_logic := '0';
signal S6 : std_logic := '0';
signal S7 : std_logic := '0';
signal S8 : std_logic := '0';
signal S9 : std_logic := '0';
--Outputs
signal Error : std_logic;

signal reset : std_logic;
signal inicio : std_logic;
signal num_bin: std_logic_vector (12 downto 0) := (others => '0');
-- Clock period definitions
constant CLK_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: fault_module_v3 PORT MAP (
CLK => CLK,
A => A,
B => B,
Cin => Cin,
S0 => S0,
S1 => S1,
S2 => S2,
S3 => S3,
S4 => S4,
S5 => S5,
S6 => S6,
S7 => S7,
S8 => S8,
S9 => S9,
Error => Error

);


-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;

-- random process
reset <= '1', '0' after 75 ns;
inicio <='0', '1' after 100 ns;

random : process(clk)
variable seed1 :positive ;
variable seed2 :positive ;
variable re1 : integer;
variable re2 : real ;
begin

if inicio = '1' then
uniform (seed1,seed2,re2);
re1 := integer (re2 * real(2**13 -1));
num_bin <= std_logic_vector ( to_unsigned (re1,13));
end if;
---wait ;
end process;

-- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for CLK_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;

--procedure RANDOM (variable Seed: inout integer; variable X: out real) is
------------------------------------------------------------------------
---- Random Number generator from:
---- The Art of Computer Systems Performance Analysis, R.Jain 1991 (p443)
---- x(n) := 7^5x(n-1) mod (2^31 - 1)
---- This has period 2^31 - 2, and it works with odd or even seeds
---- This code does not overflow for 32 bit integers.
------------------------------------------------------------------------
--constant a : integer := 16807; -- multiplier 7**5
--constant m : integer := 2147483647;-- modulus 2**31 - 1
--constant q : integer := 127773; -- m DIV a
--constant r : integer := 2836; -- m MOD a
--constant m_real : real := real(M);

--variable seed_div_q : integer;
--variable seed_mod_q : integer;
--variable new_seed : integer;

--begin
--seed_div_q := seed / q; -- truncating integer division
--seed_mod_q := seed MOD q; -- modulus
---new_seed := a * seed_mod_q - r * seed_div_q;
---if (new_seed > 0) then
---seed := new_seed;
---else
--seed := new_seed + m;
--end if;
--X := real(seed) / m_real;
--end RANDOM;
END ;
==========================================================
and its error is:mad::mad::mad::mad: :
ERROR:HDLCompiler:1156 - "C:/Users/ASUS/Desktop/v1 (1)/v1/test_bench.vhd" Line 62: Formal port <random_num> does not exist in entity <fault_module_v3>. Please compare the definition of block <fault_module_v3> to its component declaration and its instantion to detect the mismatch.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test_bench in library work failed
=========================================================
pls pls pls help me
thanks for your help
;););):(
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,754
Messages
2,569,516
Members
44,991
Latest member
Josephnag

Latest Threads

Top