Hello,
I'm trying to write VHDL code for a finite state machine that acts a controller for a circuit I am making.
The code compiles without error, and I have created a test bench to check if it works correctly. However when I run the simulation, the finite state machine remains only in the first state and does not progress to any other state.
Below is the start of the code for the finite state machine, I have omitted a lot of the repetitive parts as there are 28 states or so.
Any help from anyone in getting this working would be greatly appreciated.
Test bench:
I'm trying to write VHDL code for a finite state machine that acts a controller for a circuit I am making.
The code compiles without error, and I have created a test bench to check if it works correctly. However when I run the simulation, the finite state machine remains only in the first state and does not progress to any other state.
Below is the start of the code for the finite state machine, I have omitted a lot of the repetitive parts as there are 28 states or so.
Any help from anyone in getting this working would be greatly appreciated.
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_mach is
port(clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
mux1con, mux2con, mux3con, mux4con : out std_logic_vector(2 downto 0);
mux5con, mux6con : out std_logic_vector(1 downto 0);
mux7con, mux8con : out std_logic;
AddM1, AddM2 : out std_logic_vector(3 downto 0);
M1RW, M2RW, M1TRW, M2TRW : out std_logic;
AddM1T, AddM2T : out std_logic_vector(2 downto 0);
RomAdd : out std_logic_vector(2 downto 0));
end state_mach;
architecture rtlcode of state_mach is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27);
signal current_state : state_type;
signal next_state : state_type;
begin
------------------------
-- Setting the register
------------------------
state_register : process (clk, reset_n, next_state)
begin
if rising_edge(clk) then
if reset_n='0' then
current_state <= s0;
else
current_state <= next_state;
end if;
end if;
end process;
------------------------
-- control state machine
------------------------
control_state_machine : process (current_state)
begin
case current_state is
when s0 =>
if enable = '1' then
next_state <= s1;
else
next_state <= current_state;
end if;
...
... (repeat for all other states)
...
end case;
end process;
------------------------
-- Setting up the output
------------------------
setoutput : process (current_state)
begin
case current_state is
when s0 =>
Mux1con <= "000";
Mux2con <= "001";
Mux3con <= "111";
Mux4con <= "111";
Mux5con <= "11";
Mux6con <= "11";
Mux7con <= '1';
Mux8con <= '1';
AddM1 <= "0000";
AddM2 <= "0000";
M1RW <= '0';
M2RW <= '0';
AddM1T <= "000";
AddM2T <= "000";
M1TRW <= '0';
M2TRW <= '0';
RomAdd <= "000";
...
...(repeat for other stages)
...Test bench:
Code:
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;
entity fsm3_tb is
end entity fsm3_tb;
architecture test of fsm3_TB is
signal clk : std_logic;
signal reset_n : std_logic;
signal enable : std_logic;
signal mux1con, mux2con, mux3con, mux4con : std_logic_vector(2 downto 0);
signal mux5con, mux6con : std_logic_vector(1 downto 0);
signal mux7con, mux8con : std_logic;
signal AddM1, AddM2 : std_logic_vector(3 downto 0);
signal M1RW, M2RW, M1TRW, M2TRW : std_logic;
signal AddM1T, AddM2T : std_logic_vector(2 downto 0);
signal RomAdd : std_logic_vector(2 downto 0);
signal StopClock : boolean := FALSE;
begin
UUT: entity work.state_mach
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
mux1con => mux1con,
mux2con => mux2con,
mux3con => mux3con,
mux4con => mux4con,
mux5con => mux5con,
mux6con => mux6con,
mux7con => mux7con,
mux8con => mux8con,
AddM1 => AddM1,
AddM2 => AddM2,
M1RW => M1RW,
M2RW => M2RW,
M1TRW => M1TRW,
M2TRW => M2TRW,
RomAdd => RomAdd
);
ClockGen: process is
begin
while not StopClock loop
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end loop;
wait;
end process ClockGen;
Stim: process is
begin
wait until rising_edge(clk); -- cycle 1
enable <= '1';
wait until rising_edge(clk);
enable <= '0';
wait until rising_edge(clk); -- cycle 1
enable <= '1';
wait until rising_edge(clk);
enable <= '0';
wait until rising_edge(clk); -- cycle 1
enable <= '1';
wait until rising_edge(clk);
enable <= '0';
wait until rising_edge(clk); -- cycle 1
enable <= '1';
wait until rising_edge(clk);
enable <= '0';
wait until rising_edge(clk); -- cycle 1
enable <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
stopclock <= true;
wait;
End process;
end architecture test;