A
Ayoub
Hi everybody !
I have a small problemIo want to do a not xor for 4 input of 4 bit with input data
1 bit to have a 4 bit output using a table of input
here is my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cdm is
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
CD : in std_logic_vector(15 downto 0) ;
S : out std_logic(3 downto 0 );
end entity ;
architecture beh of cdm is
signal i :integer range 0 to 3 ;
signal idata :std_logic ;
begin
code
rocess(clk,rst)
begin
if(rst='1')then
S<='0';
i<=0 ;
idata<=data ;
else
if(clk'event and clk='1')then
type tab is array(3 downto 0)of std_logic_vector
????
??
S<=not(CD(i) xor (idata));
i<= i+1 ;
if i=3 then
idata<=data ;
end if ;
end if ;
end if ;
end process ;
end architecture ;
Thank you in advance for your answer !!
I have a small problemIo want to do a not xor for 4 input of 4 bit with input data
1 bit to have a 4 bit output using a table of input
here is my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cdm is
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
CD : in std_logic_vector(15 downto 0) ;
S : out std_logic(3 downto 0 );
end entity ;
architecture beh of cdm is
signal i :integer range 0 to 3 ;
signal idata :std_logic ;
begin
code
begin
if(rst='1')then
S<='0';
i<=0 ;
idata<=data ;
else
if(clk'event and clk='1')then
type tab is array(3 downto 0)of std_logic_vector
????
??
S<=not(CD(i) xor (idata));
i<= i+1 ;
if i=3 then
idata<=data ;
end if ;
end if ;
end if ;
end process ;
end architecture ;
Thank you in advance for your answer !!