A
Ayoub
Hi,
I have problems with my vhdl code.
can you help me plz
This is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity correla is
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic_vector(11 downto 0) ;
code: in std_logic_vector(15 downto 0 ) ;
Q
ut std_logic_vector(17 downto 0) ) ;
end entity ;
architecture arch of correla is
type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ;
signal CD : RAM;
signal temp :integer range 0 to 15;
signal idata :std_logic_vector(11 downto 0) ;
signal sum :integer range 0 to 16 ;
signal AB :integer range 0 to 17 ;
begin
CD(0)<=(code(15 downto 12));
CD(1)<=(code(11 downto 8)) ;
CD(2)<=(code(7 downto 4 ));
CD(3)<=(code(3 downto 0));
étalement
rocess(clk,rst)
begin
if(rst='1') then
Q <=(others=>'0');
temp<=0;
AB <=0;
else
if(clk'event and clk ='1') then
sum<=0;
for i in 0 to 3 loop
temp(i)<=to_integer(data(i)*CD(i)) ;
sum(i)<=sum(i) +temp(i) ;
i<= i+1 ;
if(i=3) then
idata<=data;
end if;
end loop ;
AB<=sum ;
Q<=std_logic_vector(AB) ;
end if ;
end if ;
end process ;
end architecture ;
Thanks a lot
I have problems with my vhdl code.
can you help me plz
This is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity correla is
port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic_vector(11 downto 0) ;
code: in std_logic_vector(15 downto 0 ) ;
Q
end entity ;
architecture arch of correla is
type RAM is array (0 to 3) of std_logic_vector(-8 to 7) ;
signal CD : RAM;
signal temp :integer range 0 to 15;
signal idata :std_logic_vector(11 downto 0) ;
signal sum :integer range 0 to 16 ;
signal AB :integer range 0 to 17 ;
begin
CD(0)<=(code(15 downto 12));
CD(1)<=(code(11 downto 8)) ;
CD(2)<=(code(7 downto 4 ));
CD(3)<=(code(3 downto 0));
étalement
begin
if(rst='1') then
Q <=(others=>'0');
temp<=0;
AB <=0;
else
if(clk'event and clk ='1') then
sum<=0;
for i in 0 to 3 loop
temp(i)<=to_integer(data(i)*CD(i)) ;
sum(i)<=sum(i) +temp(i) ;
i<= i+1 ;
if(i=3) then
idata<=data;
end if;
end loop ;
AB<=sum ;
Q<=std_logic_vector(AB) ;
end if ;
end if ;
end process ;
end architecture ;
Thanks a lot